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104 lines
2.0 KiB
Systemverilog
104 lines
2.0 KiB
Systemverilog
//------------------------------------------------------------------------------
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// reverse_vector_tb.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// testbench for reverse_vector module
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`timescale 1ns / 1ps
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module reverse_vector_tb();
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logic clk200;
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initial begin
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#0 clk200 = 1;
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forever
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#2.5 clk200 = ~clk200;
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end
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logic rst;
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initial begin
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#10.2 rst = 1;
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#5 rst = 0;
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//#10000;
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forever begin
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#9985 rst = ~rst;
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#5 rst = ~rst;
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end
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end
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logic nrst;
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assign nrst = ~rst;
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logic rst_once;
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initial begin // initializing non-X data before PLL starts
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#10.2 rst_once = 1;
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#5 rst_once = 0;
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end
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initial begin
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#510.2 rst_once = 1; // PLL starts at 500ns, clock appears, so doing the reset for modules
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#5 rst_once = 0;
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end
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logic nrst_once;
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assign nrst_once = ~rst_once;
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logic [31:0] DerivedClocks;
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ClkDivider #(
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.WIDTH( 32 )
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) CD1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.out( DerivedClocks[31:0] )
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);
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logic [31:0] E_DerivedClocks;
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EdgeDetect ED1[31:0] (
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.clk( {32{clk200}} ),
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.nrst( {32{nrst_once}} ),
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.in( DerivedClocks[31:0] ),
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.rising( E_DerivedClocks[31:0] ),
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.falling( ),
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.both( )
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);
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logic [15:0] RandomNumber1;
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c_rand RNG1 (
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.clk( clk200 ),
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.rst( rst_once ),
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.reseed( 1'b0 ),
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.seed_val( DerivedClocks[31:0] ),
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.out( RandomNumber1[15:0] )
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);
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logic start;
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initial begin
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#0 start = 1'b0;
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#100.2 start = 1'b1;
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#5 start = 1'b0;
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end
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// Module under test ==========================================================
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// odd width
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logic [14:0] reversed1;
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reverse_vector #(
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.WIDTH( 15 ) // WIDTH must be >=2
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) RV1 (
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.in( RandomNumber1[14:0] ),
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.out( reversed1[14:0] ) // reversed bit order
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);
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// even width
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logic [13:0] reversed2;
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reverse_vector #(
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.WIDTH( 14 ) // WIDTH must be >=2
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) RV2 (
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.in( reversed1[13:0] ),
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.out( reversed2[13:0] ) // reversed bit order
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);
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endmodule
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