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80 lines
2.2 KiB
Systemverilog
Executable File
80 lines
2.2 KiB
Systemverilog
Executable File
//------------------------------------------------------------------------------
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// round_robin_enc.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO -------------------------------------------------------------------------
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// Round robin combinational encoder to select only one bit from the input bus.
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// In contrast to priority encoder, it features cyclically changing priority
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// pointer inside, so every input bit (on aaverage) has equal chance
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// to get to the output
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//
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// This module is meant to be as simple as possible. It is possible to make
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// more efficient, but complicated circuit
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//
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// See also priority_enc.sv
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// See also round_robin_performance_enc.sv
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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round_robin_enc #(
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.WIDTH( 32 )
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) RE1 (
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.clk( clk ),
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.nrst( nrst ),
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.id( ),
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.od_valid( ),
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.od_filt( ),
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.od_bin( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module round_robin_enc #( parameter
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WIDTH = 32,
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WIDTH_W = $clogb2(WIDTH)
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)(
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input clk, // clock
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input nrst, // inversed reset, synchronous
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input [WIDTH-1:0] id, // input data bus
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output logic od_valid, // output valid (some bits are active)
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output logic [WIDTH-1:0] od_filt, // filtered data (only one priority bit active)
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output logic [WIDTH_W-1:0] od_bin // priority bit binary index
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);
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// current bit selector
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logic [WIDTH_W-1:0] priority_bit = '0;
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always_ff @(posedge clk) begin
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if( ~nrst ) begin
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priority_bit[WIDTH_W-1:0] <= '0;
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end else begin
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if( priority_bit[WIDTH_W-1:0] == WIDTH-1 ) begin
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priority_bit[WIDTH_W-1:0] <= '0;
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end else begin
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priority_bit[WIDTH_W-1:0] <= priority_bit[WIDTH_W-1:0] + 1'b1;
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end // if
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end // if nrst
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end
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always_comb begin
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if( id[priority_bit[WIDTH_W-1:0]] ) begin
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od_valid = id[priority_bit[WIDTH_W-1:0]];
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od_filt[WIDTH-1:0] = 1'b1 << priority_bit[WIDTH_W-1:0];
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od_bin[WIDTH_W-1:0] = priority_bit[WIDTH_W-1:0];
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end else begin
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od_valid = 1'b0;
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od_filt[WIDTH-1:0] = '0;
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od_bin[WIDTH_W-1:0] = '0;
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end
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end
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`include "clogb2.svh"
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endmodule
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