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122 lines
2.2 KiB
Systemverilog
Executable File
122 lines
2.2 KiB
Systemverilog
Executable File
//------------------------------------------------------------------------------
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// round_robin_performance_enc_tb.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// testbench for round_robin_performance_enc.sv module
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//
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`timescale 1ns / 1ps
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module round_robin_performance_enc_tb();
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logic clk200;
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initial begin
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#0 clk200 = 1'b0;
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forever
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#2.5 clk200 = ~clk200;
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end
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// external device "asynchronous" clock
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logic clk33a;
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initial begin
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#0 clk33a = 1'b0;
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forever
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#7 clk33a = ~clk33a;
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end
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logic clk33;
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//assign clk33 = clk33a;
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always @(*) begin
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clk33 = #($urandom_range(0, 2000)*10ps) clk33a;
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end
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logic rst;
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initial begin
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#0 rst = 1'b0;
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#10.2 rst = 1'b1;
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#5 rst = 1'b0;
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//#10000;
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forever begin
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#9985 rst = ~rst;
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#5 rst = ~rst;
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end
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end
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logic nrst;
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assign nrst = ~rst;
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logic rst_once;
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initial begin
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#0 rst_once = 1'b0;
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#10.2 rst_once = 1'b1;
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#5 rst_once = 1'b0;
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end
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logic nrst_once;
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assign nrst_once = ~rst_once;
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logic [31:0] DerivedClocks;
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clk_divider #(
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.WIDTH( 32 )
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) cd1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.ena( 1'b1 ),
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.out( DerivedClocks[31:0] )
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);
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logic [31:0] E_DerivedClocks;
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edge_detect ed1[31:0] (
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.clk( {32{clk200}} ),
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.nrst( {32{nrst_once}} ),
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.in( DerivedClocks[31:0] ),
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.rising( E_DerivedClocks[31:0] ),
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.falling( ),
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.both( )
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);
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logic [15:0] RandomNumber1;
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c_rand rng1 (
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.clk(clk200),
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.rst(rst_once),
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.reseed(1'b0),
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.seed_val(DerivedClocks[31:0]),
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.out( RandomNumber1[15:0] )
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);
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logic start;
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initial begin
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#0 start = 1'b0;
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#100 start = 1'b1;
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#20 start = 1'b0;
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end
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// Module under test ==========================================================
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`define WIDTH_W 3
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`define WIDTH (2**`WIDTH_W)
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logic [`WIDTH-1:0] pos;
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bin2pos #(
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.BIN_WIDTH( `WIDTH_W )
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) BP1 (
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.bin( RandomNumber1[`WIDTH_W-1:0] ),
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.pos( pos[`WIDTH-1:0] )
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);
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round_robin_performance_enc #(
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.WIDTH( `WIDTH )
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) RE1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.id( RandomNumber1[`WIDTH-1:0] ), //pos[`WIDTH-1:0] ),
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.od_valid( ),
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.od_filt( ),
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.od_bin( )
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);
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endmodule
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