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67 lines
1.9 KiB
Systemverilog
67 lines
1.9 KiB
Systemverilog
//--------------------------------------------------------------------------------
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// set_reset_comb.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// Synchronous SR trigger, but has a combinational output that changes
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// "with no delay" after inputs
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// No metastable state. RESET signal dominates here
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// | | +---+ | | | | | | SET
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// | | | | | | | | | |
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// +------------+ +--------------------------------+
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// | | | | | | | | | |
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// | | | | | | +---+ | | RESET
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// | | | | | | | | | |
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// +----------------------------+ +----------------+
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// | | | | | | | | | |
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// | | | +---------------+ | | Q output, original
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// | | | | | | | | | | set_reset.sv
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// +----------------+ | | | +----------------+
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// | | | | | | | | | |
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// | | +---------------+ | | | Q output, this module
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// | | | | | | | | | | set_reset_comb.sv
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// +------------+ | | | +--------------------+
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// | | | | | | | | | |
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// | | | | | | | | | |
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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set_reset_comb SR1 (
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.clk( clk ),
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.nrst( 1'b1 ),
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.s( ),
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.r( ),
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.q( ),
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.nq( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module set_reset_comb(
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input clk,
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input nrst,
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input s,
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input r,
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output q,
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output nq
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);
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logic q_reg = 0;
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always_ff @(posedge clk) begin
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if( ~nrst ) begin
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q_reg = 0;
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end else begin
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if( s ) q_reg = 1'b1;
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if( r ) q_reg = 1'b0;
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end
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end
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assign q = (s || q_reg) && ~r;
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assign nq = ~q;
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endmodule |