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65 lines
1.4 KiB
Systemverilog
65 lines
1.4 KiB
Systemverilog
//------------------------------------------------------------------------------
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// slicer_2d.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO -------------------------------------------------------------------------
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// Arbitrary slicer for 2D packed SystemVerilog arrays
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// Slices along any array edge, all array sides simultaneously
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//
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// You can also generalize this aproach to support as many dimentions as needed
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//
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// This module does NOT consume any FPGA resources though it is absolutely
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// synthesizable
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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slicer_2d #(
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.I2_HI( 3 ), .I2_LO( 0 ),
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.I1_HI( 7 ), .I1_LO( 0 ),
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.O2_HI( 2 ), .O2_LO( 1 ),
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.O1_HI( 2 ), .O1_LO( 1 )
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) S1 (
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.in ( a[3:0][7:0] ),
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.out( b[2:1][2:1] )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module slicer_2d #( parameter
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// input array shape
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I2_HI = 3, // most significant size
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I2_LO = 0,
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I1_HI = 7, // least significant size
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I1_LO = 0,
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// sliced array shape
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O2_HI = 2, // most significant size
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O2_LO = 1,
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O1_HI = 2, // least significant size
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O1_LO = 1
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)(
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input [I2_HI:I2_LO][I1_HI:I1_LO] in,
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output logic [O2_HI:O2_LO][O1_HI:O1_LO] out
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);
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integer i;
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always_comb begin
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for ( i=O2_LO; i<=O2_HI; i++ ) begin
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out[i][O1_HI:O1_LO] = in[i][O1_HI:O1_LO];
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end
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end
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endmodule
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