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88 lines
2.8 KiB
Systemverilog
88 lines
2.8 KiB
Systemverilog
//------------------------------------------------------------------------------
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// soft_latch.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// "Software" latch, aka combinational data hold circuit
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//
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// Features combinational data latching and combinational resetting
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// Zero latency for setting and resetting data
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// No hardware latches inferred by means of this circuit
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//
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// | | +---+ | | | | | | latch, this module input
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// | | | | | | | | | |
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// +------------+ +--------------------------------+
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// | | | | | | | | | |
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// +----------------------------+ +----------------+
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// | | | | | | | | | |
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// | | | | | | +---+ | | nrst, this module input
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// | | | | | | | | | |
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// +-------------------------------------------------+
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// }{A }{B }{C }{D }{E }{F }{G }{H }{J }{ in, this module data input
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// +-------------------------------------------------+
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// | | | | | | | | | |
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// | | | +---------------+ | | standard unblocking assignment
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// | | | { C | C | C | C } | |
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// +----------------+ | | | +----------------+
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// | | | | | | | | | |
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// | | +---------------+ | | | out, this module data output
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// | | { C | C | C | C } | | |
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// +------------+ | | | +--------------------+
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// | | | | | | | | | |
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// | | | | | | | | | |
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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soft_latch #(
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.WIDTH( 16 )
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) SL1 (
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.clk( clk ),
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.anrst( 1'b1 ),
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.latch( ),
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.in( ),
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.out( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module soft_latch #( parameter
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bit [7:0] WIDTH = 1 // data width
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)(
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input clk, // clock
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input anrst, // inverted reset
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input latch, // latch strobe
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input [WIDTH-1:0] in, // data in
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output logic [WIDTH-1:0] out // data out
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);
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logic [WIDTH-1:0] in_buf = '0;
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// buffering input data
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always_ff @(posedge clk or negedge anrst) begin
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if( ~anrst ) begin
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in_buf[WIDTH-1:0] <= '0;
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end else if( latch ) begin
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in_buf[WIDTH-1:0] <= in[WIDTH-1:0];
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end
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end
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// mixing combinational and buffered data to the output
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always_comb begin
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if( ~anrst ) begin
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out[WIDTH-1:0] <= '0;
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end else if( latch ) begin
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out[WIDTH-1:0] <= in[WIDTH-1:0];
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end else begin
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out[WIDTH-1:0] <= in_buf[WIDTH-1:0];
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end
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end
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endmodule
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