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https://github.com/pConst/basic_verilog.git
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149 lines
2.7 KiB
Systemverilog
149 lines
2.7 KiB
Systemverilog
//------------------------------------------------------------------------------
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// soft_latch_tb.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// testbench for soft_latch.sv module
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//
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`timescale 1ns / 1ps
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module soft_latch_tb();
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logic clk200;
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initial begin
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#0 clk200 = 1'b0;
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forever
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#2.5 clk200 = ~clk200;
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end
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// external device "asynchronous" clock
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logic clk33;
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initial begin
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#0 clk33 = 1'b0;
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forever
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#15.151 clk33 = ~clk33;
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end
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logic rst;
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initial begin
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#0 rst = 1'b0;
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#10.2 rst = 1'b1;
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#5 rst = 1'b0;
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//#10000;
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forever begin
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#9985 rst = ~rst;
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#5 rst = ~rst;
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end
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end
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logic nrst;
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assign nrst = ~rst;
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logic rst_once;
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initial begin
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#0 rst_once = 1'b0;
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#10.2 rst_once = 1'b1;
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#5 rst_once = 1'b0;
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end
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logic nrst_once;
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assign nrst_once = ~rst_once;
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logic [31:0] DerivedClocks;
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clk_divider #(
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.WIDTH( 32 )
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) cd1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.ena( 1'b1 ),
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.out( DerivedClocks[31:0] )
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);
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logic [31:0] E_DerivedClocks;
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edge_detect ed1[31:0] (
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.clk( {32{clk200}} ),
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.nrst( {32{nrst_once}} ),
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.in( DerivedClocks[31:0] ),
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.rising( E_DerivedClocks[31:0] ),
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.falling( ),
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.both( )
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);
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logic [15:0] RandomNumber1;
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c_rand rng1 (
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.clk(clk200),
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.rst(rst_once),
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.reseed(1'b0),
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.seed_val(DerivedClocks[31:0]),
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.out( RandomNumber1[15:0] )
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);
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logic start;
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initial begin
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#0 start = 1'b0;
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#100 start = 1'b1;
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#20 start = 1'b0;
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end
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// Module under test ==========================================================
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logic set;
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assign set = &RandomNumber1[14:12];
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logic ret;
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assign ret = &RandomNumber1[11:9];
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// verilog hardvare latch
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logic [15:0] data1;
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always_latch begin
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if( ret ) begin
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data1[15:0] <= '0;
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end else if( set ) begin
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data1[15:0] <= RandomNumber1[15:0];
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end
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end
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// soft_latch prototype
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logic [15:0] data2;
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set_reset_comb SR [15:0] (
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.clk( {16{clk200}} ),
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.nrst( {16{1'b1}} ),
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.s( {16{set}} & RandomNumber1[15:0] ), //set
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.r( ({16{set}} & ~RandomNumber1[15:0]) | {16{ret}} ), //rst
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.q( data2[15:0] ),
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.nq( )
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);
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// genuine soft_latch instance
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logic [15:0] data3;
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soft_latch #(
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.WIDTH( 16 )
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) SL1 (
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.clk( clk200 ),
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.nrst( ~ret ),
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.latch( set ),
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.in( RandomNumber1[15:0] ),
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.out( data3[15:0] )
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);
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//==============================================================================
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logic outputs_equal;
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assign outputs_equal = ( data1[15:0] == data2[15:0] ) &&
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( data1[15:0] == data3[15:0] );
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logic success = 1'b1;
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always_ff @(posedge clk200) begin
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if( ~nrst ) begin
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success <= 1'b1;
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end else begin
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if( ~outputs_equal ) begin
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success <= 1'b0;
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end
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end
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end
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endmodule
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