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128 lines
3.0 KiB
Systemverilog
128 lines
3.0 KiB
Systemverilog
//------------------------------------------------------------------------------
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// uart_rx.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Straightforward yet simple UART receiver implementation
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// for FPGA written in SystemVerilog
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//
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// Expects at least one stop bit
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// Features continuous data aquisition at BAUD levels up to CLK_HZ / 2
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// Features early asynchronous 'busy' reset
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//
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// see also "uart_rx.v" for equivalent Verilog version
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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uart_rx #(
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.CLK_HZ( 200_000_000 ), // in Hertz
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.BAUD( 9600 ) // max. BAUD is CLK_HZ / 2
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)(
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.clk( ),
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.nrst( ),
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.rx_data( ),
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.rx_done( ),
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.rxd( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module uart_rx #( parameter
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CLK_HZ = 200_000_000,
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BAUD = 9600,
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bit [15:0] BAUD_DIVISOR_2 = CLK_HZ / BAUD / 2
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)(
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input clk,
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input nrst,
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output logic [7:0] rx_data = '0,
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output logic rx_busy = 1'b0,
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output logic rx_done, // read strobe
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output logic rx_err,
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input rxd
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);
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// synchronizing external rxd pin to avoid metastability
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logic rxd_s;
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delay #(
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.LENGTH( 2 ),
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.WIDTH( 1 )
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) rxd_synch (
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.clk( clk ),
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.nrst( nrst ),
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.ena( 1'b1 ),
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.in( rxd ),
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.out( rxd_s )
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);
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logic start_bit_strobe;
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edge_detect rxd_fall_detector (
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.clk( clk ),
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.anrst( nrst ),
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.in( rxd_s ),
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.falling( start_bit_strobe )
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);
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logic [15:0] rx_sample_cntr = (BAUD_DIVISOR_2 - 1'b1);
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logic rx_do_sample;
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assign rx_do_sample = (rx_sample_cntr[15:0] == '0);
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// {rx_data[7:0],rx_data_9th_bit} is actually a shift register
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logic rx_data_9th_bit = 1'b0;
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always_ff @ (posedge clk) begin
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if( ~nrst ) begin
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rx_busy <= 1'b0;
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rx_sample_cntr <= (BAUD_DIVISOR_2 - 1'b1);
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{rx_data[7:0],rx_data_9th_bit} <= '0;
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end else begin
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if( ~rx_busy ) begin
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if( start_bit_strobe ) begin
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// wait for 1,5-bit period till next sample
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rx_sample_cntr[15:0] <= (BAUD_DIVISOR_2 * 3 - 1'b1);
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rx_busy <= 1'b1;
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{rx_data[7:0],rx_data_9th_bit} <= 9'b10000000_0;
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end
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end else begin
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if( rx_sample_cntr[15:0] == '0 ) begin
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// wait for 1-bit-period till next sample
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rx_sample_cntr[15:0] <= (BAUD_DIVISOR_2 * 2 - 1'b1);
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end else begin
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// counting and sampling only when 'busy'
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rx_sample_cntr[15:0] <= rx_sample_cntr[15:0] - 1'b1;
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end
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if( rx_do_sample ) begin
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if( rx_data_9th_bit == 1'b1 ) begin
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// early asynchronous 'busy' reset
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rx_busy <= 1'b0;
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end else begin
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{rx_data[7:0],rx_data_9th_bit} <= {rxd_s, rx_data[7:0]};
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end
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end
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end // ~rx_busy
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end // ~nrst
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end
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always_comb begin
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// rx_done and rx_busy fall simultaneously
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rx_done <= rx_data_9th_bit && rx_do_sample && rxd_s;
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rx_err <= rx_data_9th_bit && rx_do_sample && ~rxd_s;
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end
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endmodule
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