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98 lines
2.6 KiB
Verilog
98 lines
2.6 KiB
Verilog
//------------------------------------------------------------------------------
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// uart_tx.v
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Straightforward yet simple UART transmitter implementation
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// for FPGA written in Verilog
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//
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// One stop bit setting is hardcoded
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// Features continuous data output at BAUD levels up to CLK_HZ / 2
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// Features early asynchronous 'busy' set and reset to gain time to prepare new data
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// If multiple UartTX instances should be inferred - make tx_sample_cntr logic
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// that is common for all TX instances for effective chip area usage
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//
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// see also "uart_tx.sv" for equivalent SystemVerilog version
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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uart_tx #(
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.CLK_HZ( 200_000_000 ), // in Hertz
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.BAUD( 9600 ) // max. BAUD is CLK_HZ / 2
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) tx1 (
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.clk( ),
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.nrst( 1'b1 ),
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//.tx_do_sample( ),
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.tx_data( ),
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.tx_start( ),
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.tx_busy( ),
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.txd( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module uart_tx #( parameter
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CLK_HZ = 200_000_000,
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BAUD = 9600,
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bit [15:0] BAUD_DIVISOR = CLK_HZ / BAUD
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)(
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input clk,
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input nrst,
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//input tx_do_sample,
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input [7:0] tx_data,
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input tx_start, // write strobe
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output reg tx_busy = 1'b0,
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output reg txd = 1'b1
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);
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reg [9:0] tx_shifter = 0;
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reg [15:0] tx_sample_cntr = 0;
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always @ (posedge clk) begin
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if( (~nrst) || (tx_sample_cntr[15:0] == 0) ) begin
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tx_sample_cntr[15:0] <= (BAUD_DIVISOR-1'b1);
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end else begin
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tx_sample_cntr[15:0] <= tx_sample_cntr[15:0] - 1'b1;
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end
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end
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wire tx_do_sample;
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assign tx_do_sample = (tx_sample_cntr[15:0] == 0);
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always @ (posedge clk) begin
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if( ~nrst ) begin
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tx_busy <= 1'b0;
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tx_shifter[9:0] <= 0;
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txd <= 1'b1;
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end else begin
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if( ~tx_busy ) begin
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// asynchronous data load and 'busy' set
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if( tx_start ) begin
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tx_shifter[9:0] <= { 1'b1,tx_data[7:0],1'b0 };
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tx_busy <= 1'b1;
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end
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end else begin
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if( tx_do_sample ) begin // next bit
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// txd MUST change only on tx_do_sample although data may be loaded earlier
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{ tx_shifter[9:0],txd } <= { tx_shifter[9:0],txd } >> 1;
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// early asynchronous 'busy' reset
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if( ~|tx_shifter[9:1] ) begin
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// txd still holds data, but shifter is ready to get new info
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tx_busy <= 1'b0;
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end
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end // tx_do_sample
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end // ~tx_busy
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end // ~nrst
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end
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endmodule
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