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123 lines
3.2 KiB
Systemverilog
123 lines
3.2 KiB
Systemverilog
//------------------------------------------------------------------------------
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// uart_tx_shifter.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// UART-like shifter for simple synchronous messaging inside the FPGA or between FPGAs
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// See also `uart_rx_shifter.sv` for RX part
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//
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// TX and RX parts should share one clock source
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// Capable of continious stream transfer when tx_start is held constant 1'b1
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// Any reasonable start bit count,data bit count, stop bit count
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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uart_tx_shifter #(
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.START_BITS( 1 ),
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.DATA_BITS( 8 ),
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.STOP_BITS( 2 )
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) tx1 (
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.clk( clk ),
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.nrst( 1'b1 ),
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.tx_data( ),
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.tx_start( ),
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.tx_busy( ),
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.txd( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module uart_tx_shifter #(
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bit [7:0] START_BITS = 1, // must be >=1
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bit [7:0] DATA_BITS = 4, // must be >=1
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bit [7:0] STOP_BITS = 2 // must be >=1
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)(
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input clk, // transmitter and receiver should use
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input nrst, // the same clock
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input [DATA_BITS-1:0] tx_data, // input data get captured on write strobe
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input tx_start, // write strobe itself
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output tx_busy, // tx_busy fall on the last stop bit
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output logic txd = 1'b1
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);
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logic [DATA_BITS-1:0] tx_data_buf = '0;
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logic [7:0] state_cntr = '0;
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enum int unsigned { STOP, START, DATA } tx_state = STOP;
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always_ff @(posedge clk) begin
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if( ~nrst ) begin
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tx_state <= STOP;
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tx_data_buf[DATA_BITS-1:0] <= '0;
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state_cntr[7:0] <= '0;
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txd <= 1'b1;
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end else begin
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case( tx_state )
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STOP: begin
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txd <= 1'b1;
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if( state_cntr[7:0] != '0 ) begin
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// holding stop bits
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state_cntr[7:0]--;
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end else begin
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// idle state after stop bits
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// no need for edge detector here because tx_state changes instantly
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// after the first active tx_start cycle
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if( tx_start ) begin
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// buffering input data
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tx_data_buf[DATA_BITS-1:0] <= tx_data[DATA_BITS-1:0];
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state_cntr[7:0] <= START_BITS - 1'b1;
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tx_state <= tx_state.next();
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end // tx_start
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end // state_cntr
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end
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START: begin
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txd <= 1'b0;
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if( state_cntr[7:0] != '0 ) begin
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// holding start bits
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state_cntr[7:0]--;
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end else begin
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// transition
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state_cntr[7:0] <= DATA_BITS - 1'b1;
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tx_state <= tx_state.next();
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end // state_cntr
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end
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DATA: begin
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// setting data, MSB first
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txd <= tx_data_buf[state_cntr[7:0]];
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if( state_cntr[7:0] != '0 ) begin
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state_cntr[7:0]--;
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end else begin
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// transition
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state_cntr[7:0] <= STOP_BITS - 1'b1;
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tx_state <= tx_state.next();
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end // state_cntr
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end
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endcase // tx_state
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end
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end
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assign tx_busy = ~( (tx_state == STOP) && (state_cntr[7:0] == '0) );
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endmodule
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