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82 lines
2.9 KiB
Verilog
82 lines
2.9 KiB
Verilog
// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 01-08-2009
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module gearbox_32_33 (
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input clk,arst,
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input [31:0] din, // bit 0 is sent first
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input din_valid,
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input din_slip, // drop bit 0 of the current din
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output [32:0] dout, // bit 0 is sent first
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output reg dout_valid
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);
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reg [63:0] storage;
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reg [5:0] holding;
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// make it explicit that holding will never be greater than 32
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// to help synthesis with the shifter
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wire [63:0] aligned_din = holding[5] ?
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{din,32'b0} :
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(din << holding[4:0]);
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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holding <= 0;
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storage <= 0;
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dout_valid <= 1'b0;
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end
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else begin
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dout_valid <= 1'b0;
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if (din_valid) begin
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if (din_slip) begin
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// with 31 in and 33 out, holding decreases by 2, mod 33
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if (holding == 0) holding <= 6'd31;
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else if (holding == 1) holding <= 6'd32;
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else holding <= holding - 6'd2;
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end
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else begin
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// with 32 in and 33 out, holding decreases by 1, mod 33
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if (holding == 0) holding <= 6'd32;
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else holding <= holding - 6'd1;
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end
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// when you are holding 32 bits there is no output,
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// don't shift the storage, otherwise remove the low
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// order 33 bits.
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storage <= (holding[5] ? storage : (storage >> 6'd33)) |
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(din_slip ? (aligned_din >> 1'b1) : aligned_din);
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// the output will be valid unless we are not holding any
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// bits at all.
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dout_valid <= (holding == 0) ? 1'b0 :
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(din_slip && holding == 6'd1) ? 1'b0 :
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1'b1;
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end
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end
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end
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assign dout = storage [32:0];
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endmodule |