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133 lines
3.3 KiB
Systemverilog
133 lines
3.3 KiB
Systemverilog
// Copyright 2010 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1 ps
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// baeckler - 12-17-2008
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module scrambler_tb ();
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parameter WIDTH = 256;
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reg clk = 0, arst = 0;
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// sample data
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reg [WIDTH-1:0] data_in = 0;
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reg [15:0] cntr = 0;
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integer k = 0;
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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data_in <= 0;
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cntr <= 0;
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end
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else begin
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#1
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for (k=0; k<(WIDTH >> 4); k=k+1) begin : stim
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data_in = (data_in << 16) | cntr;
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cntr = cntr + 1'b1;
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end
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end
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end
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reg [WIDTH-1:0] last_data_in, last2_data_in;
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reg [3:0] flushing;
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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last_data_in <= 0;
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last2_data_in <= 0;
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flushing <= 4'b1111;
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end
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else begin
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last_data_in <= data_in;
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last2_data_in <= last_data_in;
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flushing <= {flushing[2:0],1'b0};
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end
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end
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// 1 bit LFSR model
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integer n;
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reg fbk;
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reg [57:0] lfsr;
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reg [WIDTH-1:0] lfsr_out;
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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lfsr_out = 0;
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lfsr = 58'h3ff_ffff_ffff_ffff;
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end
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else begin
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for (n=0; n<WIDTH; n=n+1) begin : lf
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fbk = (lfsr[57] ^ lfsr[38] ^ data_in[n]);
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lfsr = {lfsr[56:0],fbk};
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lfsr_out[n] = fbk;
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end
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end
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end
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// XOR network scrambler
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wire [WIDTH-1:0] scram_out;
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scrambler # (.WIDTH(WIDTH)) duts
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(
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.clk,
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.arst,
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.ena(1'b1),
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.din(data_in), // bit 0 is to be sent first
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.dout(scram_out)
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);
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// XOR network descrambler
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wire [WIDTH-1:0] recover_out;
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descrambler # (.WIDTH(WIDTH)) dutd
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(
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.clk,
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.arst,
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.ena(1'b1),
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.din(scram_out), // bit 0 is to be sent first
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.dout(recover_out)
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);
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reg fail = 0;
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always @(posedge clk) begin
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#1 if (lfsr_out !== scram_out) begin
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$display ("Scrambler does not match 1 bit model at time %d",$time);
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fail = 1;
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end
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if (recover_out !== last2_data_in && ~|flushing) begin
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$display ("Recovered data is not as expected at time %d",$time);
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fail = 1;
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end
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end
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// clock driver
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initial begin
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#1 arst = 1'b1;
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@(negedge clk) arst = 1'b0;
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end
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always begin
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#5 clk = ~clk;
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end
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initial begin
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#100000 if (!fail) $display ("PASS");
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$stop();
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end
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endmodule |