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144 lines
3.8 KiB
Verilog
144 lines
3.8 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 07-10-2006
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// 64-72 ECC internal RAM
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//
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module soft_ecc_ram_64bit (
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rst,
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address_a,
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address_b,
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clock_a,
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clock_b,
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data_a,
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data_b,
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wren_a,
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wren_b,
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q_a,
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q_b,
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err_a,
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err_b
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);
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`include "log2.inc"
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// Number of 64 bit data words (stored as 72 bit words internally)
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parameter NUM_WORDS = 512;
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localparam ADDR_WIDTH = log2(NUM_WORDS-1);
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// For testing error detection / correction
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// a 1 bit indicates inversion of the corresponding code bit
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// on the encoded RAM output.
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parameter PORT_A_ERROR_INJECT = 72'b0;
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parameter PORT_B_ERROR_INJECT = 72'b0;
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input rst;
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input [ADDR_WIDTH-1:0] address_a;
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input [ADDR_WIDTH-1:0] address_b;
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input clock_a;
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input clock_b;
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input [63:0] data_a;
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input [63:0] data_b;
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input wren_a;
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input wren_b;
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output [63:0] q_a;
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output [63:0] q_b;
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output [2:0] err_a;
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output [2:0] err_b;
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///////////////////////
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// port A encoder
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///////////////////////
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reg [63:0] data_a_reg;
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always @(posedge clock_a or posedge rst) begin
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if (rst) data_a_reg <= 64'b0;
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else data_a_reg <= data_a;
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end
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wire [71:0] data_a_code;
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ecc_encode_64bit enc_a (.d(data_a_reg),.c(data_a_code));
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///////////////////////
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// port B encoder
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///////////////////////
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reg [63:0] data_b_reg;
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always @(posedge clock_b or posedge rst) begin
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if (rst) data_b_reg <= 64'b0;
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else data_b_reg <= data_b;
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end
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wire [71:0] data_b_code;
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ecc_encode_64bit enc_b (.d(data_b_reg),.c(data_b_code));
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///////////////////////
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// RAM block (72 bit words)
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///////////////////////
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wire [71:0] q_a_code;
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wire [71:0] q_b_code;
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ram_block ram (
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.aclr_a(rst),
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.aclr_b(rst),
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.address_a(address_a),
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.address_b(address_b),
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.clock_a(clock_a),
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.clock_b(clock_b),
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.data_a(data_a_code),
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.data_b(data_b_code),
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.wren_a(wren_a),
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.wren_b(wren_b),
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.q_a(q_a_code),
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.q_b(q_b_code)
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);
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defparam ram .NUM_WORDS = NUM_WORDS;
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defparam ram .DAT_WIDTH = 72;
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///////////////////////
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// port A decoder
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///////////////////////
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ecc_decode_64bit dec_a (
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.clk(clock_a),
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.rst(rst),
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.c(q_a_code ^ PORT_A_ERROR_INJECT),
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.d(q_a),
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.no_err(err_a[0]),
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.err_corrected(err_a[1]),
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.err_fatal(err_a[2]));
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defparam dec_a .OUTPUT_REG = 1;
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defparam dec_a .MIDDLE_REG = 1;
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///////////////////////
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// port B decoder
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///////////////////////
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ecc_decode_64bit dec_b (
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.clk(clock_b),
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.rst(rst),
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.c(q_b_code ^ PORT_B_ERROR_INJECT),
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.d(q_b),
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.no_err(err_b[0]),
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.err_corrected(err_b[1]),
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.err_fatal(err_b[2]));
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defparam dec_b .OUTPUT_REG = 1;
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defparam dec_b .MIDDLE_REG = 1;
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endmodule
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