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66 lines
2.5 KiB
Verilog
66 lines
2.5 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 04-20-2007
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// shift "in" left until the most significant bit is a "1"
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// pass the shifted value, and number of shifts required
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// to the output.
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module scale_up (in,out,distance);
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parameter WIDTH = 16;
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parameter WIDTH_DIST = 4;
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input [WIDTH-1:0] in;
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output [WIDTH-1:0] out;
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output [WIDTH_DIST-1:0] distance;
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wire [(WIDTH_DIST+1) * WIDTH-1:0] shift_layers;
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assign shift_layers [WIDTH-1:0] = in;
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genvar i;
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generate
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for (i=0;i<WIDTH_DIST;i=i+1)
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begin : shft
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wire [WIDTH-1:0] layer_in;
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wire [WIDTH-1:0] shifted_out;
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wire [WIDTH-1:0] layer_out;
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assign layer_in = shift_layers[(i+1)*WIDTH-1:i*WIDTH];
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// are there ones in the upper part?
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wire shift_desired = ~|(layer_in[WIDTH-1:WIDTH-(1 << (WIDTH_DIST-1-i))]);
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assign distance[(WIDTH_DIST-1-i)] = shift_desired;
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// barrel shifter
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assign shifted_out = layer_in << (1 << (WIDTH_DIST-1-i));
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assign layer_out = shift_desired ? shifted_out : layer_in;
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assign shift_layers[(i+2)*WIDTH-1:(i+1)*WIDTH] = layer_out;
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end
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endgenerate
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assign out = shift_layers[(WIDTH_DIST+1)*WIDTH-1 : WIDTH_DIST*WIDTH];
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endmodule |