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43 lines
1.1 KiB
Systemverilog
43 lines
1.1 KiB
Systemverilog
//------------------------------------------------------------------------------
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// main.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Quartus benchmark project
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//
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// This project uses dynamic_delay.sv module to model both high-register count and
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// combinational-intensive design. See "Messages" tab for TOTAL time
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// spent for compilation. This will give you some quantitive charachteristic
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// of your environment processing power
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`define WIDTH 16
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`define LENGTH 1024
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`define SEL_W $clog2(`LENGTH)
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module main(
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input clk,
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input nrst,
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input [`WIDTH-1:0] id,
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input [`SEL_W-1:0] sel,
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output [`WIDTH-1:0] od
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);
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dynamic_delay #(
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.LENGTH( `LENGTH ),
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.WIDTH( 1 ),
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.SEL_W( `SEL_W )
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) dd [`WIDTH-1:0] (
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.clk( {`WIDTH{clk}} ),
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.nrst( {`WIDTH{nrst}} ),
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.ena( {`WIDTH{1'b1}} ),
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.in( id[`WIDTH-1:0] ),
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.sel( {`WIDTH{sel[`SEL_W-1:0]}} ),
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.out( od[`WIDTH-1:0] )
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);
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endmodule
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