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FPGA
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basic_verilog
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basic_verilog
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00_obsolete
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Konstantin Pavlov
2713e374c1
Lots of minor edits
2019-02-23 00:20:06 +03:00
..
ClkDivider.v
Combinational implementation of EdgeDetector with zero latency
2018-12-04 12:33:26 +03:00
DynDelay.v
snake_case naming for clock divider and main testbench template
2018-12-11 15:42:09 +03:00
EdgeDetect.sv
Combinational implementation of EdgeDetector with zero latency
2018-12-04 12:33:26 +03:00
EdgeDetect.v
Combinational implementation of EdgeDetector with zero latency
2018-12-04 12:33:26 +03:00
StaticDelay.v
snake_case naming for clock divider and main testbench template
2018-12-11 15:42:09 +03:00
