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84 lines
2.4 KiB
Verilog
84 lines
2.4 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module addsub (sub,a,b,o);
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parameter WIDTH = 16;
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parameter METHOD = 1;
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input sub;
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input [WIDTH-1:0] a,b;
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output [WIDTH:0] o;
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generate
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if (METHOD == 0) begin
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// generic style
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assign o = sub ? (a - b) : (a + b);
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end
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else if (METHOD == 1) begin
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// Hardware implementation with XORs in front of a
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// carry chain.
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wire [WIDTH+1:0] tmp;
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assign tmp = {1'b0,a,sub} + {sub,{WIDTH{sub}} ^ b,sub};
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assign o = tmp[WIDTH+1:1];
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end
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endgenerate
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endmodule
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/////////////////////////////////////
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module addsub_tb ();
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parameter WIDTH = 16;
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reg [WIDTH-1:0] a,b;
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reg sub,fail;
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wire [WIDTH:0] ox,oy;
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initial begin
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a = 0;
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b = 0;
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fail = 0;
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#100000 if (!fail) $display ("PASS");
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$stop();
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end
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addsub x (.a(a),.b(b),.sub(sub),.o(ox));
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defparam x .WIDTH = WIDTH;
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defparam x .METHOD = 0;
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addsub y (.a(a),.b(b),.sub(sub),.o(oy));
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defparam y .WIDTH = WIDTH;
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defparam y .METHOD = 1;
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always begin
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#50 a = $random;
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b = $random;
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sub = $random;
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#50
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if (ox !== oy) begin
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$display ("Mismatch at time %d",$time);
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fail = 1;
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end
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end
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endmodule
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