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70 lines
2.2 KiB
Verilog
70 lines
2.2 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module double_addsub_tb ();
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parameter WIDTH = 10;
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reg [WIDTH-1:0] a,b;
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wire [WIDTH+1:0] sum_x,sum_y,sum_z;
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reg negate_a,negate_b,fail;
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double_addsub x (.a(a),.b(b),.negate_a(negate_a),.negate_b(negate_b),.sum(sum_x));
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defparam x .WIDTH = WIDTH;
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defparam x .HW_CELLS = 1'b0;
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double_addsub y (.a(a),.b(b),.negate_a(negate_a),.negate_b(negate_b),.sum(sum_y));
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defparam y .WIDTH = WIDTH;
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defparam y .HW_CELLS = 1'b1;
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assign sum_z = (negate_a ? -a : a) + (negate_b ? -b : b);
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initial begin
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a = ~0;
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b = ~0;
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negate_a = 0;
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negate_b = 0;
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fail = 0;
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$random(123);
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end
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always begin
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#1000
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a = $random;
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b = $random;
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negate_a = $random;
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negate_b = $random;
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#1000
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if (sum_x != sum_z || sum_y != sum_z) begin
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$display ("Mismatch at time %d",$time);
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fail = 1'b1;
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end
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end
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initial begin
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#1000000
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if (!fail) $display ("PASS");
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$stop();
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end
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endmodule |