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48 lines
1.7 KiB
Verilog
48 lines
1.7 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 02-13-2006
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//
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// Three input two output compressor (full adder)
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// area cost is two 3-LUTs.
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module three_two_comp (data,sum);
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input [2:0] data;
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output [1:0] sum;
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reg [1:0] sum;
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always @(data) begin
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case (data)
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0: sum=0;
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1: sum=1;
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2: sum=1;
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3: sum=2;
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4: sum=1;
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5: sum=2;
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6: sum=2;
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7: sum=3;
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default: sum=0;
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endcase
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end
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endmodule |