mirror of
https://github.com/pConst/basic_verilog.git
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110 lines
2.1 KiB
Verilog
110 lines
2.1 KiB
Verilog
//--------------------------------------------------------------------------------
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// SimWrapper.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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//
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//
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`timescale 1ns / 1ps
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module SimWrapper();
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reg clk200;
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initial begin
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#0 clk200 = 1;
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forever
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#2.5 clk200 = ~clk200;
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end
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reg rst;
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initial begin
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#10.2 rst = 1;
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#5 rst = 0;
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//#10000;
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forever begin
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#9985 rst = ~rst;
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#5 rst = ~rst;
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end
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end
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wire nrst = ~rst;
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reg rst_once;
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initial begin // initializing non-X data before PLL starts
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#10.2 rst_once = 1;
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#5 rst_once = 0;
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end
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initial begin
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#510.2 rst_once = 1; // PLL starts at 500ns, clock appears, so doing the reset for modules
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#5 rst_once = 0;
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end
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wire nrst_once = ~rst_once;
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wire [31:0] DerivedClocks;
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ClkDivider CD1 (
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.clk(clk200),
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.nrst(nrst_once),
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.out(DerivedClocks[31:0]));
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defparam CD1.WIDTH = 32;
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wire [31:0] E_DerivedClocks;
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EdgeDetect ED1 (
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.clk(clk200),
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.nrst(nrst_once),
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.in(DerivedClocks[31:0]),
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.rising(E_DerivedClocks[31:0]),
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.falling(),
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.both()
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);
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defparam ED1.WIDTH = 32;
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wire [15:0] RandomNumber1;
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c_rand RNG1 (
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.clk(clk200),
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.rst(rst_once),
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.reseed(1'b0),
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.seed_val(DerivedClocks[31:0]),
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.out(RandomNumber1[15:0]));
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reg start;
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initial begin
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#100.2 start = 1;
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#5 start = 0;
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end
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reg [7:0] tx_sample_cntr = 0;
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always @ (posedge clk200) begin
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if (tx_sample_cntr[7:0] == 0) begin
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tx_sample_cntr[7:0] <= (173-1);
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end else begin
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tx_sample_cntr[7:0] <= tx_sample_cntr[7:0] - 1;
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end
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end
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wire tx_do_sample = (tx_sample_cntr[7:0] == 0);
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wire txd_pin;
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wire txbusy_pin;
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UartTxExtreme UT1 (
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.clk(clk200),
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.tx_do_sample(tx_do_sample),
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.tx_data(RandomNumber1[7:0]),
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.tx_start(start),
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.tx_busy(txbusy_pin),
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.txd(txd_pin)
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);
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UartRxExtreme UR1 (
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.clk(clk200),
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.rx_data(),
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.rx_busy(),
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.rx_done(),
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.rxd(txd_pin)
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);
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endmodule
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