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39 lines
837 B
Verilog
39 lines
837 B
Verilog
//--------------------------------------------------------------------------------
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// ClkDivider.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// Divides main clock to get derivative slower synchronous clocks
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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ClkDivider CD1 (
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.clk(),
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.nrst( 1'b1 ),
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.out()
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);
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defparam CD1.WIDTH = 32;
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--- INSTANTIATION TEMPLATE END ---*/
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module ClkDivider(clk,nrst,out);
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input wire clk;
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input wire nrst;
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output reg [(WIDTH-1):0] out = 0;
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parameter WIDTH = 32;
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always @ (posedge clk) begin
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if (~nrst) begin
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out[(WIDTH-1):0] <= 0;
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end
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else begin
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out[(WIDTH-1):0] <= out[(WIDTH-1):0] + 1'b1;
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end
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end
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endmodule |