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43 lines
1.7 KiB
Verilog
43 lines
1.7 KiB
Verilog
// Copyright 2008 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module iter_addsub (
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input clk,sclr,
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input first,sub,
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input a,b,
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output sum
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);
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reg car;
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assign sum = a ^ (sub ^ b) ^ (first ? sub : car);
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always @(posedge clk) begin
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if (sclr) car <= 1'b0;
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else car <= a & (sub ^ b) |
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a & (first ? sub : car) |
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(sub ^ b) & (first ? sub : car);
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end
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endmodule
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