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61 lines
2.0 KiB
Verilog
61 lines
2.0 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module equal_const_tb ();
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parameter WIDTH = 10;
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parameter CONST_VAL = 10'b1010111010;
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reg [WIDTH-1:0] dat;
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reg fail;
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wire aa,bb;
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equal_const a (.dat(dat),.out(aa));
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defparam a .WIDTH = WIDTH;
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defparam a .METHOD = 0;
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defparam a .CONST_VAL = CONST_VAL;
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equal_const b (.dat(dat),.out(bb));
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defparam b .WIDTH = WIDTH;
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defparam b .METHOD = 1;
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defparam b .CONST_VAL = CONST_VAL;
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initial begin
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dat = 0;
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fail = 0;
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#100000 if (!fail) $display ("PASS");
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$stop();
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end
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always begin
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#50 dat = {$random,$random};
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#50 if (aa !== bb) begin
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$display ("Mismatch at time %d",$time);
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fail = 1;
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end
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end
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endmodule |