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120 lines
3.2 KiB
Verilog
120 lines
3.2 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 06-13-2006
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// compare the behavior of the 128 bit data, any byte residue
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// unit to repeated single byte calls
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module crc32_128_tb ();
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////////////////////////////
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// 1 to 16 byte variable unit
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// under test
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////////////////////////////
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reg [3:0] dat_size;
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reg [31:0] crc_in;
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wire [31:0] crc_out;
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reg [127:0] dat;
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reg [127:0] tmp_dat;
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crc32_dat128_any_byte crc (
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.dat_size(dat_size),
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.crc_in(crc_in),
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.crc_out(crc_out),
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.dat8(dat[7:0]),
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.dat16(dat[15:0]),
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.dat24(dat[23:0]),
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.dat32(dat[31:0]),
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.dat40(dat[39:0]),
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.dat48(dat[47:0]),
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.dat56(dat[55:0]),
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.dat64(dat[63:0]),
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.dat72(dat[71:0]),
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.dat80(dat[79:0]),
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.dat88(dat[87:0]),
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.dat96(dat[95:0]),
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.dat104(dat[103:0]),
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.dat112(dat[111:0]),
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.dat120(dat[119:0]),
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.dat128(dat[127:0])
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);
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defparam crc .REVERSE_DATA = 1'b1; // LSB first
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////////////////////////////
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// Single byte reference
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// unit
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////////////////////////////
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reg [31:0] ref_crc_in;
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wire [31:0] ref_crc_out;
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reg [7:0] ref_dat_in;
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crc32_dat8 ref (
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.crc_in (ref_crc_in),
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.crc_out (ref_crc_out),
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.dat_in ({ref_dat_in[0],ref_dat_in[1],ref_dat_in[2],ref_dat_in[3],
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ref_dat_in[4],ref_dat_in[5],ref_dat_in[6],ref_dat_in[7]})
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);
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integer n;
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reg fail;
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initial begin
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fail = 1'b0;
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#5000000
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if (!fail) $display ("PASS");
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$stop();
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end
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always begin
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#500
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// New random stimulus
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dat = {$random,$random,$random,$random};
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crc_in = $random;
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dat_size = $random;
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#10 tmp_dat = dat;
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#10 ref_crc_in = crc_in;
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// use the ref unit to iterate through the
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// data in single bytes.
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for (n=0; n<dat_size+1; n=n+1)
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begin : spin
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ref_dat_in = tmp_dat[7:0];
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#10 if (n != dat_size) ref_crc_in = ref_crc_out;
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#10 tmp_dat = tmp_dat >> 8;
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end
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// the 128 variable and the iterated bytes
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// should get the same answer
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if (ref_crc_out != crc_out)
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begin
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$display ("Mismatch at time %d",$time);
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fail = 1'b1;
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end
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end
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endmodule |