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116 lines
5.6 KiB
Verilog
116 lines
5.6 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////
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// 2 to 6 bit ECC encoder
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//////////////////////////////////////////////
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module ecc_encode_2bit (d,c);
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input [1:0] d;
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output [5:0] c;
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wire [5:0] c;
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assign c = {d[1],d[1],d[0],d[0],^d,^d};
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endmodule
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//////////////////////////////////////////////
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// the error flag indicates
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// [2] 2 or more bit error
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// [1] 1 bit error (corrected)
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// [0] no error
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//////////////////////////////////////////////
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module ecc_decode_2bit (c,d,err_flag);
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input [5:0] c;
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output [1:0] d;
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output [2:0] err_flag;
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reg [1:0] d;
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reg [2:0] err_flag;
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always @(c) begin
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case (c)
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// bit distance to codes 0 .. 3
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6'h00 : {d,err_flag} = {2'b00, 3'b001}; // 0 4 4 4
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6'h01 : {d,err_flag} = {2'b00, 3'b010}; // 1 3 3 5
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6'h02 : {d,err_flag} = {2'b00, 3'b010}; // 1 3 3 5
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6'h03 : {d,err_flag} = {2'b00, 3'b100}; // 2 2 2 6
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6'h04 : {d,err_flag} = {2'b00, 3'b010}; // 1 3 5 3
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6'h05 : {d,err_flag} = {2'b00, 3'b100}; // 2 2 4 4
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6'h06 : {d,err_flag} = {2'b00, 3'b100}; // 2 2 4 4
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6'h07 : {d,err_flag} = {2'b01, 3'b010}; // 3 1 3 5
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6'h08 : {d,err_flag} = {2'b00, 3'b010}; // 1 3 5 3
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6'h09 : {d,err_flag} = {2'b00, 3'b100}; // 2 2 4 4
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6'h0a : {d,err_flag} = {2'b00, 3'b100}; // 2 2 4 4
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6'h0b : {d,err_flag} = {2'b01, 3'b010}; // 3 1 3 5
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6'h0c : {d,err_flag} = {2'b00, 3'b100}; // 2 2 6 2
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6'h0d : {d,err_flag} = {2'b01, 3'b010}; // 3 1 5 3
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6'h0e : {d,err_flag} = {2'b01, 3'b010}; // 3 1 5 3
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6'h0f : {d,err_flag} = {2'b01, 3'b001}; // 4 0 4 4
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6'h10 : {d,err_flag} = {2'b00, 3'b010}; // 1 5 3 3
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6'h11 : {d,err_flag} = {2'b00, 3'b100}; // 2 4 2 4
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6'h12 : {d,err_flag} = {2'b00, 3'b100}; // 2 4 2 4
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6'h13 : {d,err_flag} = {2'b10, 3'b010}; // 3 3 1 5
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6'h14 : {d,err_flag} = {2'b00, 3'b100}; // 2 4 4 2
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6'h15 : {d,err_flag} = {2'b00, 3'b100}; // 3 3 3 3
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6'h16 : {d,err_flag} = {2'b00, 3'b100}; // 3 3 3 3
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6'h17 : {d,err_flag} = {2'b01, 3'b100}; // 4 2 2 4
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6'h18 : {d,err_flag} = {2'b00, 3'b100}; // 2 4 4 2
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6'h19 : {d,err_flag} = {2'b00, 3'b100}; // 3 3 3 3
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6'h1a : {d,err_flag} = {2'b00, 3'b100}; // 3 3 3 3
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6'h1b : {d,err_flag} = {2'b01, 3'b100}; // 4 2 2 4
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6'h1c : {d,err_flag} = {2'b11, 3'b010}; // 3 3 5 1
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6'h1d : {d,err_flag} = {2'b01, 3'b100}; // 4 2 4 2
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6'h1e : {d,err_flag} = {2'b01, 3'b100}; // 4 2 4 2
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6'h1f : {d,err_flag} = {2'b01, 3'b010}; // 5 1 3 3
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6'h20 : {d,err_flag} = {2'b00, 3'b010}; // 1 5 3 3
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6'h21 : {d,err_flag} = {2'b00, 3'b100}; // 2 4 2 4
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6'h22 : {d,err_flag} = {2'b00, 3'b100}; // 2 4 2 4
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6'h23 : {d,err_flag} = {2'b10, 3'b010}; // 3 3 1 5
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6'h24 : {d,err_flag} = {2'b00, 3'b100}; // 2 4 4 2
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6'h25 : {d,err_flag} = {2'b00, 3'b100}; // 3 3 3 3
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6'h26 : {d,err_flag} = {2'b00, 3'b100}; // 3 3 3 3
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6'h27 : {d,err_flag} = {2'b01, 3'b100}; // 4 2 2 4
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6'h28 : {d,err_flag} = {2'b00, 3'b100}; // 2 4 4 2
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6'h29 : {d,err_flag} = {2'b00, 3'b100}; // 3 3 3 3
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6'h2a : {d,err_flag} = {2'b00, 3'b100}; // 3 3 3 3
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6'h2b : {d,err_flag} = {2'b01, 3'b100}; // 4 2 2 4
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6'h2c : {d,err_flag} = {2'b11, 3'b010}; // 3 3 5 1
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6'h2d : {d,err_flag} = {2'b01, 3'b100}; // 4 2 4 2
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6'h2e : {d,err_flag} = {2'b01, 3'b100}; // 4 2 4 2
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6'h2f : {d,err_flag} = {2'b01, 3'b010}; // 5 1 3 3
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6'h30 : {d,err_flag} = {2'b00, 3'b100}; // 2 6 2 2
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6'h31 : {d,err_flag} = {2'b10, 3'b010}; // 3 5 1 3
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6'h32 : {d,err_flag} = {2'b10, 3'b010}; // 3 5 1 3
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6'h33 : {d,err_flag} = {2'b10, 3'b001}; // 4 4 0 4
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6'h34 : {d,err_flag} = {2'b11, 3'b010}; // 3 5 3 1
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6'h35 : {d,err_flag} = {2'b10, 3'b100}; // 4 4 2 2
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6'h36 : {d,err_flag} = {2'b10, 3'b100}; // 4 4 2 2
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6'h37 : {d,err_flag} = {2'b10, 3'b010}; // 5 3 1 3
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6'h38 : {d,err_flag} = {2'b11, 3'b010}; // 3 5 3 1
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6'h39 : {d,err_flag} = {2'b10, 3'b100}; // 4 4 2 2
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6'h3a : {d,err_flag} = {2'b10, 3'b100}; // 4 4 2 2
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6'h3b : {d,err_flag} = {2'b10, 3'b010}; // 5 3 1 3
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6'h3c : {d,err_flag} = {2'b11, 3'b001}; // 4 4 4 0
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6'h3d : {d,err_flag} = {2'b11, 3'b010}; // 5 3 3 1
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6'h3e : {d,err_flag} = {2'b11, 3'b010}; // 5 3 3 1
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6'h3f : {d,err_flag} = {2'b01, 3'b100}; // 6 2 2 2
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endcase
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end
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endmodule
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