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286 lines
7.3 KiB
Verilog
286 lines
7.3 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 08-25-2006
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//////////////////////////////////////////
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// 8 bit to 13 bit ECC encoder
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//////////////////////////////////////////
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module ecc_encode_8bit (d,c);
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input [7:0] d;
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output [12:0] c;
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wire [12:0] c;
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assign c[0] = d[0] ^ d[1] ^ d[3] ^ d[4] ^ d[6];
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assign c[1] = d[0] ^ d[2] ^ d[3] ^ d[5] ^ d[6];
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assign c[2] = d[0];
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assign c[3] = d[1] ^ d[2] ^ d[3] ^ d[7];
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assign c[4] = d[1];
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assign c[5] = d[2];
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assign c[6] = d[3];
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assign c[7] = d[4] ^ d[5] ^ d[6] ^ d[7];
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assign c[8] = d[4];
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assign c[9] = d[5];
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assign c[10] = d[6];
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assign c[11] = d[7];
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wire [0:0] help_c12;
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xor6 help_c12_0 (help_c12[0],d[0],d[1],d[2],d[4],d[5],d[7]);
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assign c[12] = ^help_c12;
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endmodule
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//////////////////////////////////////////
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// compute a syndrome from the code word
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//////////////////////////////////////////
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module ecc_syndrome_8bit (clk,rst,c,s);
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// optional register on the outputs
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// of bits 0..6 and back one level in bit 7
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parameter REGISTER = 0;
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input clk,rst;
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input [12:0] c;
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output [4:0] s;
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reg [4:0] s;
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// 6 terms
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wire [0:0] help_s0;
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xor6 help_s0_0 (help_s0[0],c[0],c[2],c[4],c[6],c[8],c[10]);
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generate
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if (REGISTER) begin
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always @(posedge clk or posedge rst) begin
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if (rst) s[0] <= 0;
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else s[0] <= ^help_s0;
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end
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end else begin
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always @(help_s0) begin
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s[0] = ^help_s0;
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end
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end
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endgenerate
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// 6 terms
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wire [0:0] help_s1;
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xor6 help_s1_0 (help_s1[0],c[1],c[2],c[5],c[6],c[9],c[10]);
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generate
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if (REGISTER) begin
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always @(posedge clk or posedge rst) begin
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if (rst) s[1] <= 0;
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else s[1] <= ^help_s1;
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end
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end else begin
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always @(help_s1) begin
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s[1] = ^help_s1;
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end
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end
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endgenerate
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// 5 terms
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wire [0:0] help_s2;
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xor6 help_s2_0 (help_s2[0],c[3],c[4],c[5],c[6],c[11],1'b0);
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generate
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if (REGISTER) begin
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always @(posedge clk or posedge rst) begin
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if (rst) s[2] <= 0;
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else s[2] <= ^help_s2;
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end
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end else begin
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always @(help_s2) begin
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s[2] = ^help_s2;
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end
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end
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endgenerate
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// 5 terms
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wire [0:0] help_s3;
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xor6 help_s3_0 (help_s3[0],c[7],c[8],c[9],c[10],c[11],1'b0);
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generate
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if (REGISTER) begin
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always @(posedge clk or posedge rst) begin
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if (rst) s[3] <= 0;
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else s[3] <= ^help_s3;
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end
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end else begin
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always @(help_s3) begin
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s[3] = ^help_s3;
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end
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end
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endgenerate
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// 13 terms
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wire [2:0] help_s4;
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xor6 help_s4_0 (help_s4[0],c[0],c[1],c[2],c[3],c[4],c[5]);
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xor6 help_s4_1 (help_s4[1],c[6],c[7],c[8],c[9],c[10],c[11]);
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assign help_s4[2] = c[12];
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generate
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if (REGISTER) begin
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always @(posedge clk or posedge rst) begin
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if (rst) s[4] <= 0;
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else s[4] <= ^help_s4;
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end
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end else begin
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always @(help_s4) begin
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s[4] = ^help_s4;
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end
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end
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endgenerate
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endmodule
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//////////////////////////////////////////
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// From the syndrome compute the correction
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// needed to fix the data, or set fatal = 1
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// and no correction if there are too many.
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//////////////////////////////////////////
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module ecc_correction_8bit (s,e,fatal);
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input [4:0] s;
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output [7:0] e;
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output fatal;
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wire [7:0] e;
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// decode the syndrome
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reg [31:0] d;
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wire [31:0] dw /* synthesis keep */;
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always @(s) begin
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d = 32'b0;
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d[{!s[4],s[3:0]}] = 1'b1;
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end
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assign dw = d;
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// Identify uncorrectable errors
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wire fatal = (|s[3:0]) & !s[4] /* synthesis keep */;
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assign e = {
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dw[12],dw[11],dw[10],dw[9],
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dw[7],dw[6],dw[5],dw[3]
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};
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endmodule
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//////////////////////////////////////////
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// select the (uncorrected) data bits out
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// of the code word.
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//////////////////////////////////////////
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module ecc_raw_data_8bit (clk,rst,c,d);
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parameter REGISTER = 0;
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input clk,rst;
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input [12:0] c;
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output [7:0] d;
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reg [7:0] d;
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wire [7:0] d_int;
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// pull out the pure data bits
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assign d_int = {
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c[11],c[10],c[9],c[8],c[6],c[5],c[4],c[2]
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};
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// conditional output register
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generate
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if (REGISTER) begin
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always @(posedge clk or posedge rst) begin
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if (rst) d <= 0;
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else d <= d_int;
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end
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end else begin
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always @(d_int) begin
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d <= d_int;
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end
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end
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endgenerate
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endmodule
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//////////////////////////////////////////
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// 13 bit to 8 bit ECC decoder
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//////////////////////////////////////////
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module ecc_decode_8bit (clk,rst,c,d,no_err,err_corrected,err_fatal);
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// optional pipeline registers at the halfway
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// point and on the outputs
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parameter MIDDLE_REG = 0;
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parameter OUTPUT_REG = 0;
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input clk,rst;
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input [12:0] c;
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output [7:0] d;
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output no_err, err_corrected, err_fatal;
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reg [7:0] d;
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reg no_err, err_corrected, err_fatal;
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// Pull the raw (uncorrected) data from the codeword
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wire [7:0] raw_bits;
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ecc_raw_data_8bit raw (.clk(clk),.rst(rst),.c(c),.d(raw_bits));
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defparam raw .REGISTER = MIDDLE_REG;
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// Build syndrome, which will be 0 for correct
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// correct codewords, otherwise a pointer to the
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// error.
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wire [4:0] syndrome;
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ecc_syndrome_8bit syn (.clk(clk),.rst(rst),.c(c),.s(syndrome));
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defparam syn .REGISTER = MIDDLE_REG;
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// Use the the syndrome to find a correction, or 0 for no correction
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wire [7:0] err_flip;
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wire fatal;
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ecc_correction_8bit cor (.s(syndrome),.e(err_flip),.fatal(fatal));
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// Classify error types and correct data as appropriate
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// If there is a multibit error take care not to make
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// the data worse.
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generate
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if (OUTPUT_REG) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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no_err <= 1'b0;
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err_corrected <= 1'b0;
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err_fatal <= 1'b0;
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d <= 1'b0;
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end else begin
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no_err <= ~| syndrome;
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err_corrected <= syndrome[4];
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err_fatal <= fatal;
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d <= err_flip ^ raw_bits;
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end
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end
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end else begin
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always @(*) begin
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no_err = ~| syndrome;
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err_corrected = syndrome[4];
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err_fatal = fatal;
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d = err_flip ^ raw_bits;
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end
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end
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endgenerate
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endmodule
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