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114 lines
3.1 KiB
Verilog
114 lines
3.1 KiB
Verilog
// Copyright 2008 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 03-28-2008
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module chain_delay_adjust
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(
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clk,rst,
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calibrate_a,
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calibrate_b,
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a_wins,
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b_wins,
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valid,
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adjusting,
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current_stats
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);
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parameter CALIBRATE_BITS = 4;
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input clk,rst;
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output [CALIBRATE_BITS-1:0] calibrate_a;
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output [CALIBRATE_BITS-1:0] calibrate_b;
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input a_wins,b_wins,valid;
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output [15:0] current_stats;
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output reg adjusting;
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reg [2*CALIBRATE_BITS-1:0] current_setting;
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reg [7:0] trials,a_tally,b_tally;
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reg [15:0] current_stats;
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assign {calibrate_a, calibrate_b} = current_setting;
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reg [2:0] state /* synthesis preserve */;
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parameter
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ST_START = 3'h0,
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ST_COUNT = 3'h1,
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ST_CHECK = 3'h2,
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ST_CHECK_B = 3'h3,
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ST_ADJUST = 3'h4,
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ST_OPERATE = 3'h5;
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always @(posedge clk) begin
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if (rst) begin
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state <= ST_START;
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a_tally <= 0;
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b_tally <= 0;
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trials <= 0;
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current_setting <= 0;
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current_stats <= 0;
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adjusting <= 1'b1;
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end
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else begin
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case (state)
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ST_START: begin
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state <= ST_COUNT;
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end
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ST_COUNT: begin
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if (valid & a_wins) a_tally <= a_tally + 1'b1;
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if (valid & b_wins) b_tally <= b_tally + 1'b1;
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if (valid) trials <= trials + 1'b1;
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if (&trials) state <= ST_CHECK;
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end
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ST_CHECK : begin
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current_stats <= {a_tally,b_tally};
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a_tally <= 0;
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b_tally <= 0;
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trials <= 0;
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state <= ST_CHECK_B;
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end
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ST_CHECK_B : begin
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if ((current_stats[15:8] != 8'hff &&
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current_stats[15:8] != 8'h00) ||
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(current_stats[7:0] != 8'hff &&
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current_stats[7:0] != 8'h00))
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begin
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state <= ST_OPERATE;
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end
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else begin
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state <= ST_ADJUST;
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end
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end
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ST_ADJUST : begin
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adjusting <= 1'b1;
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current_setting <= current_setting + 1'b1;
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state <= ST_COUNT;
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end
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ST_OPERATE : begin
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adjusting <= 1'b0;
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state <= ST_COUNT;
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end
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endcase
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end
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end
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endmodule |