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102 lines
2.8 KiB
Systemverilog
102 lines
2.8 KiB
Systemverilog
// Copyright 2011 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module rx_buffer_fifo_2_tb ();
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parameter WIDTH = 16;
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reg clk = 0,arst = 0;
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reg [WIDTH-1:0] din;
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wire [WIDTH-1:0] dout;
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reg din_valid;
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wire dout_valid;
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reg dout_wait;
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wire overflow;
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reg [WIDTH-1:0] junk = 0;
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rx_buffer_fifo_2 dut
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(
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.clk,
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.arst,
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.din(din_valid ? din : junk),
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.din_valid, // pulse marking fresh input data
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.dout_wait, // wait means I don't want to see dout_valid yet
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.dout,
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.dout_valid, // pulse marking fresh output data
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.overflow // overflow with loss of data
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);
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defparam dut .WIDTH = WIDTH;
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always begin
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#5 clk = ~clk;
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end
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initial begin
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#1 arst = 1'b1;
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@(negedge clk) arst = 0;
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end
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reg [1:0] rbits = 0;
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reg fail = 0;
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reg [WIDTH-1:0] expected_dout;
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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din <= 0;
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expected_dout <= 1;
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din_valid <= 0;
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dout_wait <= 0;
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end
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else begin
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rbits <= $random;
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junk <= $random;
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// provide data on the input side
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if (rbits[0]) begin
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din_valid <= 1'b1;
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din <= din + 1'b1;
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end
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else begin
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din_valid <= 1'b0;
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end
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dout_wait <= rbits[1];
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// grab data on the output side
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if (!overflow & !dout_wait & dout_valid) begin
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if (dout !== expected_dout) begin
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$display ("Mismatch at time %d",$time);
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fail = 1;
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end
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expected_dout <= expected_dout + 1'b1;
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end
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end
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end
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// this is obviously only OK for simulation
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always @(posedge clk) begin
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#2 if (overflow) begin
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arst = 1'b1;
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@(negedge clk) arst = 1'b0;
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end
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end
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endmodule |