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95 lines
3.0 KiB
Verilog
95 lines
3.0 KiB
Verilog
// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 01-08-2009
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module gearbox_32_66 (
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input clk,arst,
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input [31:0] din, // bit 0 is sent first
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input din_valid,
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input slip_to_frame,
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output [65:0] dout, // bit 0 is sent first
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output dout_valid,
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// this is the number of bit slips used to find the lock
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// intended for debug / test
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output reg [6:0] slip_count
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);
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////////////////////////////////////
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// workhorse 32 to 33 unit
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reg gb33_slip;
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wire [32:0] gb33_dout;
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wire gb33_dout_valid;
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gearbox_32_33 gb33 (
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.clk(clk),
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.arst(arst),
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.din(din), // bit 0 is sent first
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.din_valid(din_valid),
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.din_slip(gb33_slip), // drop bit 0 of the current din
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.dout(gb33_dout), // bit 0 is sent first
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.dout_valid(gb33_dout_valid)
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);
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wire correct_framing = ^gb33_dout[1:0];
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////////////////////////////////////
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// alternate 33 bit halves with slip control
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reg first_half;
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reg [32:0] prev_word;
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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first_half <= 1'b1;
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gb33_slip <= 1'b0;
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prev_word <= 33'b0;
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slip_count <= 7'h0;
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end
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else begin
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if (din_valid) gb33_slip <= 1'b0;
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// alternate reading 33 bit halves
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if (gb33_dout_valid) begin
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first_half <= ~first_half;
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if (first_half) prev_word <= gb33_dout;
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end
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// when in search mode check the framing bits
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// they should be different if the alignment
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// is correct.
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if (slip_to_frame) begin
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if (gb33_dout_valid & first_half & !correct_framing) begin
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// this isn't right, do a slip
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gb33_slip <= 1'b1;
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slip_count <= slip_count + 1'b1;
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end
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end
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end
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end
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assign dout = {gb33_dout,prev_word};
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assign dout_valid = gb33_dout_valid & !first_half;
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endmodule |