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96 lines
2.7 KiB
Systemverilog
96 lines
2.7 KiB
Systemverilog
// Copyright 2010 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1 ps
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module gearbox_66_20_tb ();
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reg clk = 0 ;
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reg [65:0] din = 0;
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wire din_ack;
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wire [19:0] dout_20;
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gearbox_66_20 dut_a (
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.clk,
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.sclr(1'b0),
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.din, // lsbit sent first
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.din_ack,
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.dout(dout_20)
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);
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reg [39:0] history;
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always @(posedge clk) begin
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history <= (history >> 20) | (dout_20 << 20);
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end
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wire [19:0] shifted_dout_20 = history >> 3;
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wire [65:0] recovered;
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wire recovered_valid;
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gearbox_20_66 dut_b (
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.clk,
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.slip_to_frame (1'b1), // look for ethernet framing, [1:0] opposite
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.din(shifted_dout_20), // lsbit used first
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.dout(recovered),
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.dout_valid(recovered_valid)
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);
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reg [63:0] payload;
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initial payload = {$random,$random};
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always @(posedge clk) begin
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if (din_ack) begin
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din <= {payload,2'b10};
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payload <= {payload[62:0],payload[63]};
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end
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end
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reg [65:0] last_recover = 0;
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reg recover_err = 1'b1;
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always @(posedge clk) begin
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if (recovered_valid) begin
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last_recover <= recovered;
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recover_err <= (recovered[65:2] !== {last_recover[64:2],last_recover[65]}) ?
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1'b1 : 1'b0;
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end
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end
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always begin
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#5 clk = ~clk;
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end
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reg grace = 1'b1;
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initial begin
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grace = 1'b1;
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#10000 grace = 1'b0;
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end
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reg fail = 1'b0;
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always @(posedge clk) begin
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if (!grace & recover_err) fail <= 1'b1;
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end
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initial begin
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#100000 if (!fail) $display ("PASS");
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$stop();
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end
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endmodule |