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92 lines
2.6 KiB
Systemverilog
92 lines
2.6 KiB
Systemverilog
// Copyright 2010 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module gearbox_66_40_tb ();
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reg clk = 1'b0;
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reg [65:0] din = 0; // lsbit first
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reg sclr = 1'b0;
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wire din_ack;
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wire [39:0] dout;
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wire din_pre_ack;
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wire din_pre2_ack;
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gearbox_66_40 dut_a (.*);
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reg [79:0] history = 0;
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always @(posedge clk) begin
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history <= {dout,history[79:40]};
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end
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wire [39:0] word_locked,slipping;
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genvar i;
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generate
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for (i=0; i<40; i=i+1) begin
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wire [65:0] recover;
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wire recover_valid;
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gearbox_40_66 dut_b (
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.clk,
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.slip_to_frame(1'b1),
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.din (history[i+39:i]),
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.dout (recover),
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.dout_valid (recover_valid),
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.slipping(slipping[i]),
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.word_locked (word_locked[i])
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);
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end
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endgenerate
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reg send_rand = 1'b1;
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reg [31:0] cntr = 0;
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always @(posedge clk) begin
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if (din_ack) din <= send_rand ? {$random,$random,din[13],din[13]^1'b1} :
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{30'h0,cntr,2'b00,2'b01};
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end
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wire all_locked = &word_locked;
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reg fail = 1'b0;
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initial begin
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#100 @(posedge all_locked);
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@(negedge all_locked);
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$display ("Unexpected loss of lock");
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fail = 1'b1;
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end
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initial begin
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@(posedge all_locked);
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$display ("locked at time %d",$time);
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send_rand = 1'b0;
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#100000 if (!fail) $display ("PASS");
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$stop();
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end
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always begin
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#5 clk <= ~clk;
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end
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endmodule
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