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75 lines
2.4 KiB
Verilog
75 lines
2.4 KiB
Verilog
// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 01-22-2009
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// accept 2 words, output in single words
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// send the less significant end through first
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module two_to_one #(
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parameter WORD_LEN = 33
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)
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(
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input clk,arst,
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input [2*WORD_LEN-1:0] din,
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input din_valid,
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output din_ready,
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output [WORD_LEN-1:0] dout,
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input dout_ready,
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output dout_valid
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);
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reg [1:0] holding; // holding 0..2 words
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reg [2*WORD_LEN-1:0] storage;
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assign din_ready =
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(holding == 2'b0) ||
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((holding == 2'b1) && dout_ready);
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assign dout_valid = (|holding);
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assign dout = storage[WORD_LEN-1:0];
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always @(posedge clk or posedge arst) begin
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if (arst) begin
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storage <= 0;
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holding <= 0;
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end
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else begin
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if (din_ready & din_valid) begin
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// if we are reloading it goes to 2 blocks available
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storage <= din;
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holding <= 2'b10;
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end
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else begin
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// not reloading
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// if the output side is ready lose one block
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if (dout_valid & dout_ready) begin
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holding <= holding - 1'b1;
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storage <= {{(WORD_LEN){1'b0}},
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storage[2*WORD_LEN-1:WORD_LEN]};
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end
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end
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end
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end
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endmodule
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