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94 lines
4.2 KiB
Verilog
94 lines
4.2 KiB
Verilog
// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module x4_encoder_8b10b (
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input clk,
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input rst,
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input [3:0] kin_ena, // Data in is a special code, not all are legal.
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input [31 : 0] ein_dat, // 8b data in
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output [39 : 0] eout_dat // data out
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);
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parameter METHOD = 1;
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wire [3:0] eout_rdcomb;
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wire [3:0] eout_rdreg;
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wire [3:0] eout_val; // not used, since ein_ena not used in cascaded version
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encoder_8b10b enc3(
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.clk (clk),
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.rst (rst),
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.kin_ena(kin_ena[3]), // Data in is a special code, not all are legal.
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.ein_ena(1'b1), // Data (or code) input enable
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.ein_dat(ein_dat[31 : 24]), // 8b data in
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.ein_rd(eout_rdreg[0]), // running disparity input
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.eout_val(eout_val[3]), // data out is valid
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.eout_dat(eout_dat[39 : 30]), // data out
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.eout_rdcomb(eout_rdcomb[3]), // running disparity output (comb)
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.eout_rdreg(eout_rdreg[3]) // running disparity output (reg)
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);
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defparam enc3.METHOD = METHOD;
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encoder_8b10b enc2(
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.clk (clk),
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.rst (rst),
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.kin_ena(kin_ena[2]), // Data in is a special code, not all are legal.
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.ein_ena(1'b1), // Data (or code) input enable
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.ein_dat(ein_dat[23 : 16]), // 8b data in
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.ein_rd(eout_rdcomb[3]), // running disparity input
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.eout_val(eout_val[2]), // data out is valid
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.eout_dat(eout_dat[29 : 20]), // data out
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.eout_rdcomb(eout_rdcomb[2]), // running disparity output (comb)
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.eout_rdreg(eout_rdreg[2]) // running disparity output (reg)
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);
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defparam enc2.METHOD = METHOD;
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encoder_8b10b enc1(
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.clk (clk),
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.rst (rst),
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.kin_ena(kin_ena[1]), // Data in is a special code, not all are legal.
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.ein_ena(1'b1), // Data (or code) input enable
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.ein_dat(ein_dat[15 : 8]), // 8b data in
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.ein_rd(eout_rdcomb[2]), // running disparity input
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.eout_val(eout_val[1]), // data out is valid
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.eout_dat(eout_dat[19 : 10]), // data out
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.eout_rdcomb(eout_rdcomb[1]), // running disparity output (comb)
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.eout_rdreg(eout_rdreg[1]) // running disparity output (reg)
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);
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defparam enc1.METHOD = METHOD;
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encoder_8b10b enc0(
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.clk (clk),
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.rst (rst),
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.kin_ena(kin_ena[0]), // Data in is a special code, not all are legal.
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.ein_ena(1'b1), // Data (or code) input enable
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.ein_dat(ein_dat[7 : 0]), // 8b data in
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.ein_rd(eout_rdcomb[1]), // running disparity input
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.eout_val(eout_val[0]), // data out is valid
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.eout_dat(eout_dat[9 : 0]), // data out
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.eout_rdcomb(eout_rdcomb[0]), // running disparity output (comb)
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.eout_rdreg(eout_rdreg[0]) // running disparity output (reg)
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);
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defparam enc0.METHOD = METHOD;
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endmodule
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