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96 lines
3.3 KiB
Verilog
96 lines
3.3 KiB
Verilog
// Copyright 2011 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps / 1 ps
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// baeckler - 02-19-2008
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// Monitor the frequency in KHz of (n) clock signals
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//
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module frequency_monitor #(
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parameter NUM_SIGNALS = 4,
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parameter REF_KHZ = 20'd156250
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)
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(
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input [NUM_SIGNALS-1:0] signal,
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input ref_clk,
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output [20*NUM_SIGNALS-1:0] khz_counters
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);
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// Divide reference clock to make a 1 KHz pulse
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reg [19:0] ref_cntr = 0;
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reg ref_cntr_max = 1'b0;
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always @(posedge ref_clk) begin
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ref_cntr_max <= (ref_cntr == (REF_KHZ-2));
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if (ref_cntr_max) ref_cntr <= 0;
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else ref_cntr <= ref_cntr + 1'b1;
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end
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// Divide by 1000 to create a seconds pulse
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reg [9:0] khz_cntr = 0;
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reg khz_cntr_max = 1'b0;
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always @(posedge ref_clk) begin
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khz_cntr_max <= (khz_cntr == 10'd999) && ref_cntr_max;
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if (khz_cntr_max) khz_cntr <= 0;
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else if (ref_cntr_max) khz_cntr <= khz_cntr + 1'b1;
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end
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wire one_second = khz_cntr_max;
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genvar i;
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generate
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for (i=0; i<NUM_SIGNALS; i=i+1) begin : cn
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// scale the signal down from MHz range to KHz range
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reg [9:0] prescale = 0;
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reg prescale_max = 0;
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reg scaled_toggle = 0 /* synthesis preserve */
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/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_false_path -from [get_keepers *frequency_monitor*scaled_toggle]\" " */;
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always @(posedge signal[i]) begin
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prescale_max <= (prescale == 10'd998);
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if (prescale_max) prescale <= 0;
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else prescale <= prescale + 1'b1;
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if (prescale_max) scaled_toggle <= ~scaled_toggle;
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end
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// synchronize to reference domain
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reg [4:0] capture = 0 /* synthesis preserve */;
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always @(posedge ref_clk) begin
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capture <= {capture [3:0],scaled_toggle};
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end
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// tally KHz of signal activity over a 1s window
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reg [19:0] tally = 0,last_tally = 0;
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always @(posedge ref_clk) begin
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if (one_second) begin
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tally <= 0;
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last_tally <= tally;
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end
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else if (capture[4] ^ capture[3]) tally <= tally + 1'b1;
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end
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assign khz_counters[(i+1)*20-1:i*20] = last_tally;
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end
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endgenerate
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endmodule |