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211 lines
6.2 KiB
Verilog
211 lines
6.2 KiB
Verilog
// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module quad_stream_grabber #(
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parameter DAT_WIDTH = 72, // multiple of 8
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parameter ADDR_BITS = 8 // depth of the sample memory
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)
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(
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// streams to observe - independently clocked
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input [3:0] clk_str, arst_str,
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input [DAT_WIDTH*4-1:0] data_in,
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input [3:0] data_in_valid,
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// system clk / ctrl
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input clk_sys, arst_sys,
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input start_harvest,
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// combined output
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output [7:0] dout,
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input dout_ready,
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output dout_valid,
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output reporting
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);
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localparam NUM_STREAMS = 4;
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wire [NUM_STREAMS*8-1:0] byte_out_str ;
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wire [NUM_STREAMS-1:0] byte_out_ready_str, byte_out_valid_str;
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wire [NUM_STREAMS*8-1:0] rdata_sys;
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wire [NUM_STREAMS-1:0] rdata_ready_sys, rdata_valid_sys;
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wire [NUM_STREAMS-1:0] start_harvest_str;
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// register the harvest start signal on sys domain
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reg start_harvest_r /* synthesis preserve */;
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always @(posedge clk_sys or posedge arst_sys) begin
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if (arst_sys) start_harvest_r <= 0;
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else start_harvest_r <= start_harvest;
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end
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wire [NUM_STREAMS-1:0] reporting_str,reporting_sys;
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reg [NUM_STREAMS-1:0] reporting_str_r;
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genvar i;
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generate
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for (i=0;i<NUM_STREAMS;i=i+1)
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begin : fl
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///////////////////////////////////////////
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// move harvest to this stream domain
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///////////////////////////////////////////
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reg [1:0] hsync /* synthesis preserve */;
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always @(posedge clk_str[i] or posedge arst_str[i]) begin
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if (arst_str[i]) hsync <= 0;
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else hsync <= {hsync[0],start_harvest_r};
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end
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assign start_harvest_str[i] = hsync[1];
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///////////////////////////////////////////
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// move reporting out of this stream domain
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///////////////////////////////////////////
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always @(posedge clk_str[i] or posedge arst_str[i]) begin
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if (arst_str[i]) reporting_str_r[i] <= 0;
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else reporting_str_r[i] <= reporting_str[i];
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end
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reg [1:0] rsync /* synthesis preserve */;
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always @(posedge clk_sys or posedge arst_sys) begin
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if (arst_sys) rsync <= 0;
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else rsync <= {rsync[0],reporting_str_r[i]};
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end
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assign reporting_sys[i] = rsync[1];
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///////////////////////////////////////////
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// capture and byte serializer per stream
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///////////////////////////////////////////
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stream_grabber sg (
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.clk(clk_str[i]),
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.arst(arst_str[i]),
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.data_in(data_in[DAT_WIDTH*(i+1)-1:DAT_WIDTH*i]),
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.data_in_valid(data_in_valid[i]),
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.start_harvest(start_harvest_str[i]),
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.reporting(reporting_str[i]),
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.byte_out(byte_out_str[8*(i+1)-1:8*i]),
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.byte_out_valid(byte_out_valid_str[i]),
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.byte_out_ready(byte_out_ready_str[i])
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);
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defparam sg .INITIAL_SR_CONTENT = {"Stream 0" | i,8'h0};
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defparam sg .INITIAL_HOLDING = 8;
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defparam sg .DAT_WIDTH = DAT_WIDTH;
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defparam sg .ADDR_BITS = ADDR_BITS;
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///////////////////////////////////////////
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// cross to the system domain per stream
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///////////////////////////////////////////
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clock_crossing_fifo ccf
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(
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.wrclk(clk_str[i]),
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.wdata_valid(byte_out_valid_str[i]),
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.wdata(byte_out_str[8*(i+1)-1:8*i]),
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.wdata_ready(byte_out_ready_str[i]),
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.rdclk(clk_sys),
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.rdata_ready(rdata_ready_sys[i]),
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.rdata(rdata_sys[8*(i+1)-1:8*i]),
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.rdata_valid(rdata_valid_sys[i])
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);
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defparam ccf .DAT_WIDTH = 8;
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defparam ccf .WORDS = 8;
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end
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endgenerate
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/////////////////////////
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// combine streams 0,1
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/////////////////////////
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wire [7:0] dout0;
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wire dout_ready0,dout_valid0,reporting0;
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stream_mux sm0 (
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.clk(clk_sys), .arst(arst_sys),
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.din_a(rdata_sys[8*(0+1)-1:8*0]),
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.din_ready_a(rdata_ready_sys[0]),
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.din_valid_a(rdata_valid_sys[0]),
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.reporting_a(reporting_sys[0]),
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.din_b(rdata_sys[8*(1+1)-1:8*1]),
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.din_ready_b(rdata_ready_sys[1]),
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.din_valid_b(rdata_valid_sys[1]),
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.reporting_b(reporting_sys[1]),
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.start_harvest(start_harvest),
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.reporting(reporting0),
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.dout_ready(dout_ready0),
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.dout_valid(dout_valid0),
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.dout(dout0)
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);
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defparam sm0 .WIDTH = 8;
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/////////////////////////
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// combine streams 2,3
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/////////////////////////
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wire [7:0] dout1;
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wire dout_ready1,dout_valid1,reporting1;
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stream_mux sm1 (
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.clk(clk_sys), .arst(arst_sys),
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.din_a(rdata_sys[8*(2+1)-1:8*2]),
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.din_ready_a(rdata_ready_sys[2]),
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.din_valid_a(rdata_valid_sys[2]),
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.reporting_a(reporting_sys[2]),
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.din_b(rdata_sys[8*(3+1)-1:8*3]),
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.din_ready_b(rdata_ready_sys[3]),
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.din_valid_b(rdata_valid_sys[3]),
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.reporting_b(reporting_sys[3]),
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.start_harvest(start_harvest),
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.reporting(reporting1),
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.dout_ready(dout_ready1),
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.dout_valid(dout_valid1),
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.dout(dout1)
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);
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defparam sm1 .WIDTH = 8;
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/////////////////////////
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// combine pairs 01,23
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/////////////////////////
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stream_mux sm2 (
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.clk(clk_sys), .arst(arst_sys),
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.din_a(dout0),
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.din_ready_a(dout_ready0),
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.din_valid_a(dout_valid0),
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.reporting_a(reporting0),
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.din_b(dout1),
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.din_ready_b(dout_ready1),
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.din_valid_b(dout_valid1),
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.reporting_b(reporting1),
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.start_harvest(start_harvest),
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.reporting(reporting),
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.dout_ready(dout_ready),
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.dout_valid(dout_valid),
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.dout(dout)
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);
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defparam sm2 .WIDTH = 8;
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endmodule |