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124 lines
3.7 KiB
Verilog
124 lines
3.7 KiB
Verilog
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 02-14-2006
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//
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// Stratix II 8:1 MUX showing
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// Two 7-LUT implementation
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// Two 5-LUTs, one 7-LUT implementation
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// Generic implementation
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//
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// Both methods cost two packed ALM's
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// they have slightly different speed and routing
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// properties. 77 is currently used by default.
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module eight_to_one (dat,sel,out);
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parameter SEVEN_SEVEN_STYLE = 1'b0;
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parameter FIVE_FIVE_STYLE = 1'b0;
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input [7:0] dat;
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input [2:0] sel;
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output out;
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wire out;
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generate
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if (SEVEN_SEVEN_STYLE) begin
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wire cell_tail;
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stratixii_lcell_comb lc_tail (
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.datae(sel[1]),
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.dataf(sel[2]),
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.datad(sel[0]),
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.dataa(dat[1]),
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.datac(dat[0]),
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.datab(dat[3]),
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.datag(dat[2]),
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.combout(cell_tail),
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.cout(),.shareout(),.sumout(),.cin(1'b0),.sharein(1'b0));
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defparam lc_tail .extended_lut = "on";
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defparam lc_tail .lut_mask = 64'hff00ff00ccf0aaf0;
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stratixii_lcell_comb lc_head (
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.datae(sel[1]),
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.dataf(cell_tail),
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.datad(sel[2]),
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.dataa(dat[5]),
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.datac(dat[4]),
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.datab(dat[7]),
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.datag(dat[6]),
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.combout(out),
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.cout(),.shareout(),.sumout(),.cin(1'b0),.sharein(1'b0));
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defparam lc_head .extended_lut = "on";
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defparam lc_head .lut_mask = 64'hccffaafff000f000;
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end
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else if (FIVE_FIVE_STYLE) begin
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wire m0_out, m1_out;
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stratixii_lcell_comb m0 (
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.dataa(sel[0]),
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.datab(sel[1]),
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.datac(dat[0]),
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.datad(dat[1]),
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.datae(dat[2]),
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.combout(m0_out),
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.dataf(1'b0),.datag(1'b1),
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.cout(),.shareout(),.sumout(),.cin(1'b0),.sharein(1'b0));
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defparam m0 .shared_arith = "off";
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defparam m0 .extended_lut = "off";
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defparam m0 .lut_mask = 64'h7654321076543210;
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stratixii_lcell_comb m1 (
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.dataa(sel[0]),
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.datab(sel[1]),
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.datac(dat[4]),
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.datad(dat[5]),
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.datae(dat[6]),
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.dataf(1'b0),.datag(1'b1),
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.combout(m1_out),
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.cout(),.shareout(),.sumout(),.cin(1'b0),.sharein(1'b0));
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defparam m1 .shared_arith = "off";
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defparam m1 .extended_lut = "off";
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defparam m1 .lut_mask = 64'h7654321076543210;
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stratixii_lcell_comb head (
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.dataa(sel[0]),
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.datab(sel[1]),
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.datac(dat[3]),
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.datad(m0_out),
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.datae(sel[2]),
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.dataf(m1_out),
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.datag(dat[7]),
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.combout(out),
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.cout(),.shareout(),.sumout(),.cin(1'b0),.sharein(1'b0));
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defparam head .shared_arith = "off";
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defparam head .extended_lut = "on";
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defparam head .lut_mask = 64'hF7F7F7808080F780;
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end
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else begin
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// let the compiler select style
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assign out = dat[sel];
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end
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endgenerate
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endmodule |