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52 lines
2.0 KiB
Verilog
52 lines
2.0 KiB
Verilog
// Copyright 2010 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler 01-27-2010
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// #delay the bus randomly by 0..7 increments of the delay parameter
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`timescale 1 ps / 1 ps
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module random_delay #(
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parameter D_INCREMENT = 100,
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parameter WIDTH = 8
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)(
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input [WIDTH-1:0] din,
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output reg [WIDTH-1:0] dout
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);
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reg [2:0] delay_sel;
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initial delay_sel = $random;
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always @(*) begin
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case (delay_sel)
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3'h0 : dout = din;
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3'h1 : dout = #D_INCREMENT din;
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3'h2 : dout = #(D_INCREMENT*2) din;
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3'h3 : dout = #(D_INCREMENT*3) din;
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3'h4 : dout = #(D_INCREMENT*4) din;
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3'h5 : dout = #(D_INCREMENT*5) din;
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3'h6 : dout = #(D_INCREMENT*6) din;
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3'h7 : dout = #(D_INCREMENT*7) din;
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endcase
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end
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endmodule
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