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47 lines
1.3 KiB
Verilog
47 lines
1.3 KiB
Verilog
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM32X1S.v,v 1.8 2005/03/14 22:32:58 yanx Exp $
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///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995/2004 Xilinx, Inc.
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// All Right Reserved.
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 8.1i (I.13)
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// \ \ Description : Xilinx Functional Simulation Library Component
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// / / Static Synchronous RAM 32-Deep by 1-Wide
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// /___/ /\ Filename : RAM32X1S.v
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// \ \ / \ Timestamp : Thu Mar 25 16:43:33 PST 2004
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// \___\/\___\
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//
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// Revision:
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// 03/23/04 - Initial version.
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// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block;
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// End Revision
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`timescale 1 ps / 1 ps
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module RAM32X1S (O, A0, A1, A2, A3, A4, D, WCLK, WE);
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parameter INIT = 32'h00000000;
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output O;
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input A0, A1, A2, A3, A4, D, WCLK, WE;
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reg [31:0] mem;
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wire [4:0] adr;
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assign adr = {A4, A3, A2, A1, A0};
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assign O = mem[adr];
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initial
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mem = INIT;
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always @(posedge WCLK)
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if (WE == 1'b1)
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mem[adr] <= #100 D;
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endmodule
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