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85 lines
2.2 KiB
Verilog
85 lines
2.2 KiB
Verilog
/*
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Copyright (c) 2004, 2006 Pablo Bleyer Kocik.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. The name of the author may not be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED
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WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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PacoBlaze uclock test implementation
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*/
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`include "timescale_inc.v"
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`include "pacoblaze_inc.v"
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module uclock_ti(
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MCKO,
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nRST,
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A, D,
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IOA
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);
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input MCKO, nRST;
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input [23:0] A;
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input [15:0] D;
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inout [13:0] IOA;
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wire clk, rst, ir; // clock, reset, interrupt req
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wire [`code_depth-1:0] ad; // instruction address
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wire [`operand_width-1:0] pa, po; // port id, port out
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wire rd, wr, ia; // read strobe, write strobe, interrupt ack
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wire [`code_width-1:0] di;
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wire [`operand_width-1:0] pi;
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assign clk = MCKO;
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assign rst = !nRST;
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assign pi = D[7:0];
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assign IOA[7:0] = po;
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assign IOA[8] = 'hz;
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assign ir = IOA[8];
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uclock rom(
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.clk(clk),
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.address(ad),
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.instruction(di)
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);
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pacoblaze dut(
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.clk(clk),
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.reset(rst),
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.address(ad),
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.instruction(di),
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.port_id(pa),
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.read_strobe(rd),
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.write_strobe(wr),
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.in_port(pi),
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.out_port(po),
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.interrupt(ir),
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.interrupt_ack(ia)
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);
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endmodule
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