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55 lines
1.4 KiB
Verilog
55 lines
1.4 KiB
Verilog
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDRSE.v,v 1.8.38.1 2005/11/02 19:31:18 yanx Exp $
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///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995/2004 Xilinx, Inc.
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// All Right Reserved.
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 8.1i (I.24)
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// \ \ Description : Xilinx Functional Simulation Library Component
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// / / D Flip-Flop with Synchronous Reset and Set and Clock Enable
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// /___/ /\ Filename : FDRSE.v
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// \ \ / \ Timestamp : Thu Mar 25 16:42:18 PST 2004
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// \___\/\___\
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//
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// Revision:
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// 03/23/04 - Initial version.
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// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block.
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// 10/20/05 - Add set & reset check to main block. (CR219794)
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// End Revision
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`timescale 1 ps / 1 ps
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module FDRSE (Q, C, CE, D, R, S);
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parameter INIT = 1'b0;
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output Q;
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reg Q;
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input C, CE, D, R, S;
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tri0 GSR = glbl.GSR;
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initial Q = 0;
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always @(GSR)
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if (GSR)
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assign Q = INIT;
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else
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deassign Q;
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always @(posedge C )
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if (GSR== 0) begin
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if (R)
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Q <= #100 0;
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else if (S)
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Q <= #100 1;
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else if (CE)
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Q <= #100 D;
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end
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endmodule
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