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77 lines
2.0 KiB
Verilog
77 lines
2.0 KiB
Verilog
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LUT4.v,v 1.6 2005/03/14 22:32:54 yanx Exp $
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///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995/2004 Xilinx, Inc.
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// All Right Reserved.
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 8.1i (I.13)
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// \ \ Description : Xilinx Functional Simulation Library Component
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// / / 4-input Look-Up-Table with General Output
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// /___/ /\ Filename : LUT4.v
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// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004
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// \___\/\___\
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//
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// Revision:
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// 03/23/04 - Initial version.
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// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf.
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// End Revision
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`timescale 100 ps / 10 ps
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module LUT4 (O, I0, I1, I2, I3);
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parameter INIT = 16'h0000;
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input I0, I1, I2, I3;
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output O;
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reg O;
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reg tmp;
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always @( I3 or I2 or I1 or I0 ) begin
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tmp = I0 ^ I1 ^ I2 ^ I3;
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if ( tmp == 0 || tmp == 1)
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O = INIT[{I3, I2, I1, I0}];
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else
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O = lut4_mux4 ( {lut4_mux4 ( INIT[15:12], {I1, I0}),
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lut4_mux4 ( INIT[11:8], {I1, I0}),
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lut4_mux4 ( INIT[7:4], {I1, I0}),
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lut4_mux4 ( INIT[3:0], {I1, I0}) }, {I3, I2});
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end
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function lut4_mux4;
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input [3:0] d;
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input [1:0] s;
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begin
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if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
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lut4_mux4 = d[s];
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else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]))
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lut4_mux4 = d[0];
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else if ((s[1] == 0) && (d[0] === d[1]))
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lut4_mux4 = d[0];
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else if ((s[1] == 1) && (d[2] === d[3]))
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lut4_mux4 = d[2];
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else if ((s[0] == 0) && (d[0] === d[2]))
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lut4_mux4 = d[0];
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else if ((s[0] == 1) && (d[1] === d[3]))
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lut4_mux4 = d[1];
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else
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lut4_mux4 = 1'bx;
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end
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endfunction
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endmodule
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