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41 lines
1.1 KiB
Verilog
41 lines
1.1 KiB
Verilog
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXCY.v,v 1.8 2005/03/14 22:32:55 yanx Exp $
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///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995/2004 Xilinx, Inc.
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// All Right Reserved.
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 8.1i (I.13)
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// \ \ Description : Xilinx Functional Simulation Library Component
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// / / 2-to-1 Multiplexer for Carry Logic with General Output
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// /___/ /\ Filename : MUXCY.v
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// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004
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// \___\/\___\
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//
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// Revision:
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// 03/23/04 - Initial version.
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// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end;
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// End Revision
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`timescale 100 ps / 10 ps
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module MUXCY (O, CI, DI, S);
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output O;
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reg O;
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input CI, DI, S;
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always @(CI or DI or S) begin
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if (S)
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O <= CI;
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else
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O <= DI;
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end
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endmodule
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