2.1 KiB
basic_verilog
Some basic must-have verilog modules
(licensed under CC BY-SA 4_0)
CONTENTS:
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/Advanced Synthesis Cookbook/ - useful code from Altera's cookbook
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/KCPSM6_Release9_30Sept14/ - Xilinx's Picoblaze soft processor
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/pacoblaze-2.2/ - version of Picoblaze adapted for Altera devices
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Main_tb.v - basic testbench template
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ActionBurst - multichannel one-shot triggering module
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ActionBurst2 - multichannel one-shot triggering with variable steps module
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bin2pos - converts binary coded value to positional (one-hot) code
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ClkDivider - wide reference clock divider
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DeBounce - two-cycle debounce for input buttons
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DynDelay - dynamic delay for arbitrary input signal made on general-purpose trigger elements
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EdgeDetect - edge detector, gives one-tick pulses on every signal edge
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Encoder - digital encoder input logic module
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fifo - single-clock FIFO buffer (queue) implementation
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NDivide - primitive integer divider
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lifo - single-clock LIFO buffer (stack) implementation
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PulseGen - generates pulses with given width and delay
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bin2pos - converts positional (one-hot) value to binary representation
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ResetSet - SR trigger variant w/o metastable state, set dominates here
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ReverseVector - reverses signal order within multi-bit bus
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SetReset - SR trigger variant w/o metastable state, reset dominates here
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StaticDelay - static delay for arbitrary input signal made on Xilinx`s SRL16E primitives. Also serves as input synchronizer, a standard way to get rid of metastability issues
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UartRx - straightforward yet simple UART receiver implementation for FPGA written in Verilog
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UartTx - straightforward yet simple UART transmitter implementation for FPGA written in Verilog
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UartRxExtreme - extreme minimal UART receiver implementation for FPGA written in Verilog
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UartTxExtreme - extreme minimal UART transmitter implementation for FPGA written in Verilog
Also added some simple testbenches for selected modules
Author: Konstantin Pavlov, pavlovconst@gmail.com