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98 lines
2.1 KiB
Verilog
98 lines
2.1 KiB
Verilog
//--------------------------------------------------------------------------------
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// NDivide.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// Primitive integer divider
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// Unsigned inputs, y should be < or == x
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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NDivide ND1 (
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.clk( ),
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.nrst( 1'b1 ),
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.d_start( ),
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.d_busy( ),
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.d_done( ),
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.x( ),
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.y( ),
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.q( ),
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.r( )
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);
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defparam ND1.XBITS = 32;
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defparam ND1.YBITS = 32;
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--- INSTANTIATION TEMPLATE END ---*/
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module NDivide(clk,nrst,d_start,d_busy,d_done,x,y,q,r);
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parameter XBITS = 32;
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parameter YBITS = 32;
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input wire clk;
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input wire nrst;
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input wire d_start;
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output reg d_busy = 0;
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output wire d_done;
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input wire [(XBITS-1):0] x;
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input wire [(YBITS-1):0] y;
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output reg [(XBITS-1):0] q = 0;
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output wire [(YBITS-1):0] r;
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reg [(XBITS+YBITS-1):0] x_buf = 0;
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reg [(YBITS-1):0] y_buf = 0;
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reg [31:0] i = 0;
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wire [(YBITS+XBITS-1):0] shift_y;
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wire [(YBITS+XBITS-1):0] x_buf_sub_shift_y;
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assign
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shift_y[(YBITS+XBITS-1):0] = y_buf[(YBITS-1):0] << i[31:0],
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x_buf_sub_shift_y[(YBITS+XBITS-1):0] = x_buf[(YBITS+XBITS-1):0] - shift_y[(YBITS+XBITS-1):0];
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always @ (posedge clk) begin
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if (~nrst) begin
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q[(XBITS-1):0] <= 0;
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i[31:0] <= 0;
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x_buf[(XBITS+YBITS-1):0] <= 0;
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y_buf[(YBITS-1):0] <= 0;
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d_busy <= 0;
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end else begin
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if (~d_busy) begin
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if (d_start) begin
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i[31:0] <= (XBITS-1);
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x_buf[(XBITS+YBITS-1):0] <= x[(XBITS-1):0];
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y_buf[(YBITS-1):0] <= y[(YBITS-1):0];
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d_busy <= 1;
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end // d_start
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end else begin
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// this condition means crossing of zero boundary
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if (x_buf_sub_shift_y[(YBITS+XBITS-1):0] > x_buf[(XBITS+YBITS-1):0]) begin
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q[i[31:0]] <= 0;
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end else begin
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q[i[31:0]] <= 1;
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x_buf[(XBITS+YBITS-1):0] <= x_buf_sub_shift_y[(YBITS+XBITS-1):0];
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end
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if (i[31:0] != 0) begin
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i[31:0] <= i[31:0] - 1;
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end else begin
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d_busy <= 0;
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end
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end // ~d_busy
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end // ~nrst
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end
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assign
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d_done = d_busy && ( i[31:0] == 0 ),
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r[(XBITS-1):0] = x_buf[(XBITS+YBITS-1):0];
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endmodule
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