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56 lines
2.7 KiB
Markdown
56 lines
2.7 KiB
Markdown
# basic_verilog
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### Some basic must-have verilog modules
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(licensed under CC BY-SA 4_0)
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Author: Konstantin Pavlov, pavlovconst@gmail.com
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### CONTENTS:
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* **/Advanced Synthesis Cookbook/** - useful code from Altera's cookbook
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* **/KCPSM6_Release9_30Sept14/** - Xilinx's Picoblaze soft processor
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* **/pacoblaze-2.2/** - version of Picoblaze adapted for Altera devices
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* **/scripts/** - useful TCL scripts
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* **/scripts/compile.tcl** - Modelsim no-project-mode compile script
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* **/scripts/quartus_custom_report.tcl** - custom reporting or report analisys for Intel Quartus IDE
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* **/scripts/quartus_system_console_init.tcl** - initialization script for reading/writing Avalon-MM through JTAG-to-Avalon-MM bridge IP
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* **/scripts/write_avalon_mm_from_file.tcl** - writing bulk binary data from binary file to Avalon-MM through JTAG-to-Avalon-MM bridge IP
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* **main_tb.sv** - basic testbench template
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* **ActionBurst** - multichannel one-shot triggering module
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* **ActionBurst2** - multichannel one-shot triggering with variable steps module
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* **bin2pos** - converts binary coded value to positional (one-hot) code
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* **clk_divider** - wide reference clock divider
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* **debounce** - two-cycle debounce for input buttons
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* **dynamic_delay** - dynamic delay for arbitrary input signal made on general-purpose trigger elements
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* **edge_detect** - edge detector, gives one-tick pulses on every signal edge
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* **encoder** - digital encoder input logic module
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* **fifo** - single-clock FIFO buffer (queue) implementation
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* **NDivide** - primitive integer divider
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* **lifo** - single-clock LIFO buffer (stack) implementation
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* **leave_one_hot** - leaves only lowest hot bit in vector
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* **PulseGen** - generates pulses with given width and delay
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* **pos2bin** - converts positional (one-hot) value to binary representation
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* **reset_set** - SR trigger variant w/o metastable state, set dominates here
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* **reverse_vector** - reverses signal order within multi-bit bus
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* **set_reset** - SR trigger variant w/o metastable state, reset dominates here
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* **spi_master** - universal spi master module
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* **delay** - static delay for arbitrary input signal made on Xilinx`s SRL16E primitives. Also serves as input synchronizer, a standard way to get rid of metastability issues
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* **UartRx** - straightforward yet simple UART receiver implementation for FPGA written in Verilog
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* **UartTx** - straightforward yet simple UART transmitter implementation for FPGA written in Verilog
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* **UartRxExtreme** - extreme minimal UART receiver implementation for FPGA written in Verilog
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* **UartTxExtreme** - extreme minimal UART transmitter implementation for FPGA written in Verilog
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Also added testbenches for selected modules
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