mirror of
https://github.com/pConst/basic_verilog.git
synced 2025-01-14 06:42:54 +08:00
292 lines
12 KiB
Tcl
292 lines
12 KiB
Tcl
# TCL File Generated by Component Editor 8.0
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# Sat May 31 20:41:17 PDT 2008
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# DO NOT MODIFY
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# +-----------------------------------
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# | module burst_read_master
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# |
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set_module_property DESCRIPTION "Custom Avalon-MM Masters"
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set_module_property NAME master_template
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set_module_property VERSION 1.0
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set_module_property GROUP "Templates"
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set_module_property AUTHOR JCJB
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set_module_property ICON_PATH ALTERA_LOGO_ANIM.gif
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set_module_property DISPLAY_NAME master_template
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set_module_property TOP_LEVEL_HDL_FILE custom_master.v
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set_module_property TOP_LEVEL_HDL_MODULE custom_master
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE false
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set_module_property SIMULATION_MODEL_IN_VERILOG false
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set_module_property SIMULATION_MODEL_IN_VHDL false
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set_module_property SIMULATION_MODEL_HAS_TULIPS false
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set_module_property SIMULATION_MODEL_IS_OBFUSCATED false
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# |
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# +-----------------------------------
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set_module_property ELABORATION_CALLBACK elaborate_me
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set_module_property VALIDATION_CALLBACK validate_me
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# +-----------------------------------
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# | files
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# |
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add_file custom_master.v {SYNTHESIS SIMULATION}
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add_file burst_write_master.v {SYNTHESIS SIMULATION}
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add_file burst_read_master.v {SYNTHESIS SIMULATION}
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add_file write_master.v {SYNTHESIS SIMULATION}
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add_file latency_aware_read_master.v {SYNTHESIS SIMULATION}
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | parameters
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# |
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# Avalon Master Settings
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add_parameter MASTER_DIRECTION Integer 0 "Sets the master direction between read (0) and write (1) transfers"
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set_parameter_property MASTER_DIRECTION VISIBLE true
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set_parameter_property MASTER_DIRECTION DISPLAY_NAME "Master Direction"
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set_parameter_property MASTER_DIRECTION GROUP "Avalon-MM Master Properties"
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set_parameter_property MASTER_DIRECTION AFFECTS_PORT_WIDTHS true
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set_parameter_property MASTER_DIRECTION ALLOWED_RANGES {"0:Read" "1:Write"}
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add_parameter DATA_WIDTH Integer 32 "Width of the data path"
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set_parameter_property DATA_WIDTH VISIBLE true
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set_parameter_property DATA_WIDTH DISPLAY_NAME "Data Width"
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set_parameter_property DATA_WIDTH GROUP "Avalon-MM Master Properties"
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set_parameter_property DATA_WIDTH AFFECTS_PORT_WIDTHS true
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set_parameter_property DATA_WIDTH ALLOWED_RANGES {8 16 32 64 128 256 512 1024}
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add_parameter ADDRESS_WIDTH Integer "32" "Address Width"
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set_parameter_property ADDRESS_WIDTH VISIBLE true
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set_parameter_property ADDRESS_WIDTH DISPLAY_NAME "Address Width"
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set_parameter_property ADDRESS_WIDTH GROUP "Avalon-MM Master Properties"
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set_parameter_property ADDRESS_WIDTH AFFECTS_PORT_WIDTHS true
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set_parameter_property ADDRESS_WIDTH ALLOWED_RANGES {32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 9 8 7 6 5 4}
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# Burst Settings
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add_parameter BURST_CAPABLE Integer 0 "Enable bursting"
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set_parameter_property BURST_CAPABLE VISIBLE true
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set_parameter_property BURST_CAPABLE DISPLAY_NAME "Burst Capable"
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set_parameter_property BURST_CAPABLE GROUP "Burst Properties"
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set_parameter_property BURST_CAPABLE AFFECTS_PORT_WIDTHS true
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set_parameter_property BURST_CAPABLE ALLOWED_RANGES {"0:Disabled" "1:Enabled"}
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add_parameter MAXIMUM_BURST_COUNT Integer "2" "Maximum Burst Count"
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set_parameter_property MAXIMUM_BURST_COUNT VISIBLE true
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set_parameter_property MAXIMUM_BURST_COUNT DISPLAY_NAME "Maximum Burst Count"
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set_parameter_property MAXIMUM_BURST_COUNT GROUP "Burst Properties"
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set_parameter_property MAXIMUM_BURST_COUNT AFFECTS_PORT_WIDTHS false
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set_parameter_property MAXIMUM_BURST_COUNT ALLOWED_RANGES {1 2 4 8 16 32 64 128}
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add_parameter BURST_COUNT_WIDTH Integer "2" "Enable bursting"
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set_parameter_property BURST_COUNT_WIDTH VISIBLE false
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set_parameter_property BURST_COUNT_WIDTH DISPLAY_NAME "Burst Count Width"
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set_parameter_property BURST_COUNT_WIDTH GROUP "Burst Properties"
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set_parameter_property BURST_COUNT_WIDTH AFFECTS_PORT_WIDTHS true
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set_parameter_property BURST_COUNT_WIDTH ALLOWED_RANGES {1:8}
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# Other Settings
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add_parameter FIFO_DEPTH Integer "32" "FIFO depth"
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set_parameter_property FIFO_DEPTH VISIBLE true
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set_parameter_property FIFO_DEPTH DISPLAY_NAME "FIFO Depth"
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set_parameter_property FIFO_DEPTH GROUP "Other Properties"
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set_parameter_property FIFO_DEPTH AFFECTS_PORT_WIDTHS false
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set_parameter_property FIFO_DEPTH ALLOWED_RANGES {4 8 16 32 64 128 256}
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add_parameter FIFO_DEPTH_LOG2 Integer "5" "log2(FIFO Depth)"
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set_parameter_property FIFO_DEPTH_LOG2 VISIBLE false
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set_parameter_property FIFO_DEPTH_LOG2 DISPLAY_NAME "log2(FIFO Depth)"
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set_parameter_property FIFO_DEPTH_LOG2 GROUP "Other Properties"
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set_parameter_property FIFO_DEPTH_LOG2 AFFECTS_PORT_WIDTHS false
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set_parameter_property FIFO_DEPTH_LOG2 ALLOWED_RANGES {2:8}
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add_parameter MEMORY_BASED_FIFO Integer 1 "Select false if you want register based (0) FIFO instead of memory (1)"
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set_parameter_property MEMORY_BASED_FIFO VISIBLE true
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set_parameter_property MEMORY_BASED_FIFO DISPLAY_NAME "Memory based FIFO"
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set_parameter_property MEMORY_BASED_FIFO GROUP "Other Properties"
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set_parameter_property MEMORY_BASED_FIFO AFFECTS_PORT_WIDTHS false
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set_parameter_property MEMORY_BASED_FIFO ALLOWED_RANGES {"1:Memory" "0:Logic"}
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | connection point clock_reset
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# |
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add_interface clock_reset clock end
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set_interface_property clock_reset ptfSchematicName ""
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add_interface_port clock_reset clk clk Input 1
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add_interface_port clock_reset reset reset Input 1
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | connection point avalon_master
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# |
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add_interface avalon_master avalon start
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set_interface_property avalon_master linewrapBursts false
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set_interface_property avalon_master adaptsTo ""
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set_interface_property avalon_master doStreamReads false
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set_interface_property avalon_master doStreamWrites false
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set_interface_property avalon_master burstOnBurstBoundariesOnly false
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set_interface_property avalon_master ASSOCIATED_CLOCK clock_reset
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add_interface_port avalon_master master_address address Output -1
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add_interface_port avalon_master master_read read Output 1
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add_interface_port avalon_master master_write write Output 1
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add_interface_port avalon_master master_byteenable byteenable Output -1
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add_interface_port avalon_master master_readdata readdata Input -1
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add_interface_port avalon_master master_readdatavalid readdatavalid Input 1
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add_interface_port avalon_master master_writedata writedata Output -1
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add_interface_port avalon_master master_burstcount burstcount Output -1
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add_interface_port avalon_master master_waitrequest waitrequest Input 1
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | connection point control
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# |
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add_interface control conduit end
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set_interface_property control ASSOCIATED_CLOCK clock_reset
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add_interface_port control control_fixed_location export Input 1
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add_interface_port control control_read_base export Input -1
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add_interface_port control control_write_base export Input -1
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add_interface_port control control_read_length export Input -1
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add_interface_port control control_write_length export Input -1
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add_interface_port control control_go export Input 1
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add_interface_port control control_done export Output 1
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add_interface_port control control_early_done export Output 1
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | connection point user
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# |
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add_interface user conduit end
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set_interface_property user ASSOCIATED_CLOCK clock_reset
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add_interface_port user user_read_buffer export Input 1
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add_interface_port user user_buffer_output_data export Output -1
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add_interface_port user user_data_available export Output 1
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add_interface_port user user_write_buffer export Input 1
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add_interface_port user user_buffer_input_data export Input -1
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add_interface_port user user_buffer_full export Output 1
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# |
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# +-----------------------------------
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proc elaborate_me {} {
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# set all the new port widths
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set the_data_width [get_parameter_value DATA_WIDTH]
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set the_byteenable_width [expr {$the_data_width / 8} ]
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set the_address_width [get_parameter_value ADDRESS_WIDTH]
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set the_burst_count_width [get_parameter_value BURST_COUNT_WIDTH]
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set_port_property control_read_base WIDTH $the_address_width
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set_port_property control_read_length WIDTH $the_address_width
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set_port_property control_write_base WIDTH $the_address_width
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set_port_property control_write_length WIDTH $the_address_width
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set_port_property user_buffer_input_data WIDTH $the_data_width
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set_port_property user_buffer_output_data WIDTH $the_data_width
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set_port_property master_address WIDTH $the_address_width
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set_port_property master_byteenable WIDTH $the_byteenable_width
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set_port_property master_readdata WIDTH $the_data_width
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set_port_property master_writedata WIDTH $the_data_width
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set_port_property master_burstcount WIDTH $the_burst_count_width
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# determine the master direction and burst capabilities
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set the_master_direction [get_parameter_value MASTER_DIRECTION]
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set the_burst_capable [get_parameter_value BURST_CAPABLE]
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# switch between read and write master signals (excluding burstcount)
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if { $the_master_direction == 0 } {
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set_port_property control_read_base TERMINATION false
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set_port_property control_read_length TERMINATION false
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set_port_property control_write_base TERMINATION true
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set_port_property control_write_length TERMINATION true
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set_port_property control_early_done TERMINATION false
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set_port_property user_read_buffer TERMINATION false
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set_port_property user_write_buffer TERMINATION true
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set_port_property user_buffer_input_data TERMINATION true
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set_port_property user_buffer_output_data TERMINATION false
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set_port_property user_data_available TERMINATION false
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set_port_property user_buffer_full TERMINATION true
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set_port_property master_read TERMINATION false
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set_port_property master_write TERMINATION true
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set_port_property master_readdata TERMINATION false
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set_port_property master_readdatavalid TERMINATION false
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set_port_property master_writedata TERMINATION true
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} else {
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set_port_property control_read_base TERMINATION true
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set_port_property control_read_length TERMINATION true
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set_port_property control_write_base TERMINATION false
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set_port_property control_write_length TERMINATION false
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set_port_property control_early_done TERMINATION true
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set_port_property user_read_buffer TERMINATION true
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set_port_property user_write_buffer TERMINATION false
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set_port_property user_buffer_input_data TERMINATION false
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set_port_property user_buffer_output_data TERMINATION true
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set_port_property user_data_available TERMINATION true
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set_port_property user_buffer_full TERMINATION false
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set_port_property master_read TERMINATION true
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set_port_property master_write TERMINATION false
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set_port_property master_readdata TERMINATION true
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set_port_property master_readdatavalid TERMINATION true
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set_port_property master_writedata TERMINATION false
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}
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# enable/disable the burstcount signal
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if { $the_burst_capable == 0 } {
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set_port_property master_burstcount TERMINATION true
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} else {
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set_port_property master_burstcount TERMINATION false
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}
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}
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proc validate_me {} {
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# read in all the parameter that matter for validation
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set the_burst_capable [get_parameter_value BURST_CAPABLE]
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set the_maximum_burst_count [get_parameter_value MAXIMUM_BURST_COUNT]
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set the_fifo_depth [get_parameter_value FIFO_DEPTH]
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# when burst is enabled check to make sure FIFO depth is at least twice as large (also enable/disable burst count)
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if { $the_burst_capable == 1 } {
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set_parameter_property MAXIMUM_BURST_COUNT ENABLED true
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if { $the_fifo_depth < [expr {$the_maximum_burst_count * 2}] } {
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send_message Error "The FIFO Depth must be at least twice as large as Maximum Burst Count."
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}
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} else {
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set_parameter_property MAXIMUM_BURST_COUNT ENABLED false
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}
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set the_burst_count [get_parameter_value MAXIMUM_BURST_COUNT]
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set the_burst_count_width [expr {(log($the_burst_count) / log(2)) + 1}]
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set the_fifo_depth [get_parameter_value FIFO_DEPTH]
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set the_fifo_depth_log2 [expr {log($the_fifo_depth) / log(2)}]
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set_parameter_value BURST_COUNT_WIDTH $the_burst_count_width
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set_parameter_value FIFO_DEPTH_LOG2 $the_fifo_depth_log2
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}
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