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102 lines
4.1 KiB
Verilog
102 lines
4.1 KiB
Verilog
// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module x4_decoder_8b10b (
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input clk,
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input rst,
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input [39:0] din_dat, // 10b data input
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output [31:0] dout_dat, // data out
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output [3:0] dout_k, // special code
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output [3:0] dout_kerr, // coding mistake detected
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output [3:0] dout_rderr, // running disparity mistake detected
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output [3:0] dout_rdcomb, // running dispartiy output (comb)
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output [3:0] dout_rdreg // running disparity output (reg)
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);
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parameter METHOD = 1;
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decoder_8b10b dec3(
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.clk (clk),
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.rst (rst),
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.din_ena(1'b1), // Data (or code) input enable
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.din_dat(din_dat[39 : 30]), // 8b data in
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.din_rd(dout_rdreg[0]), // running disparity input
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.dout_val(),
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.dout_kerr(dout_kerr[3]),
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.dout_dat(dout_dat[31 : 24]), // data out
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.dout_k(dout_k[3]),
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.dout_rderr(dout_rderr[3]),
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.dout_rdcomb(dout_rdcomb[3]), // running disparity output (comb)
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.dout_rdreg(dout_rdreg[3]) // running disparity output (reg)
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);
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defparam dec3.METHOD = METHOD;
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decoder_8b10b dec2(
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.clk (clk),
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.rst (rst),
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.din_ena(1'b1), // Data (or code) input enable
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.din_dat(din_dat[29 : 20]), // 8b data in
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.din_rd(dout_rdcomb[3]), // running disparity input
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.dout_val(),
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.dout_kerr(dout_kerr[2]),
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.dout_dat(dout_dat[23 : 16]), // data out
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.dout_k(dout_k[2]),
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.dout_rderr(dout_rderr[2]),
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.dout_rdcomb(dout_rdcomb[2]), // running disparity output (comb)
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.dout_rdreg(dout_rdreg[2]) // running disparity output (reg)
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);
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defparam dec2.METHOD = METHOD;
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decoder_8b10b dec1(
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.clk (clk),
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.rst (rst),
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.din_ena(1'b1), // Data (or code) input enable
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.din_dat(din_dat[19 : 10]), // 8b data in
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.din_rd(dout_rdcomb[2]), // running disparity input
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.dout_val(),
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.dout_kerr(dout_kerr[1]),
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.dout_dat(dout_dat[15 : 8]), // data out
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.dout_k(dout_k[1]),
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.dout_rderr(dout_rderr[1]),
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.dout_rdcomb(dout_rdcomb[1]), // running disparity output (comb)
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.dout_rdreg(dout_rdreg[1]) // running disparity output (reg)
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);
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defparam dec1.METHOD = METHOD;
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decoder_8b10b dec0(
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.clk (clk),
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.rst (rst),
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.din_ena(1'b1), // Data (or code) input enable
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.din_dat(din_dat[9 : 0]), // 8b data in
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.din_rd(dout_rdcomb[1]), // running disparity input
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.dout_val(),
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.dout_kerr(dout_kerr[0]),
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.dout_dat(dout_dat[7 : 0]), // data out
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.dout_k(dout_k[0]),
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.dout_rderr(dout_rderr[0]),
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.dout_rdcomb(dout_rdcomb[0]), // running disparity output (comb)
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.dout_rdreg(dout_rdreg[0]) // running disparity output (reg)
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);
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defparam dec0.METHOD = METHOD;
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endmodule
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