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118 lines
3.3 KiB
Systemverilog
118 lines
3.3 KiB
Systemverilog
// Copyright 2011 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module quad_stream_grabber_tb ();
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parameter DAT_WIDTH = 72; // multiple of 8
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parameter ADDR_BITS = 4; // depth of the sample memory
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// streams to observe - independently clocked
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wire [3:0] clk_str;
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reg [3:0] arst_str;
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reg [DAT_WIDTH*4-1:0] data_in;
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reg [3:0] data_in_valid = 4'hf;
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// system clk / ctrl
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reg clk_sys, arst_sys;
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reg start_harvest;
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// combined output
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wire [7:0] dout;
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reg dout_ready = 1'b1;
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reg dout_valid;
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reg reporting;
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quad_stream_grabber dut
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(
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.*
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);
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defparam dut .DAT_WIDTH = DAT_WIDTH; // multiple of 8
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defparam dut .ADDR_BITS = ADDR_BITS; // depth of the sample memory
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//////////////////////////////////////////////////
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// rough test data
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//////////////////////////////////////////////////
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genvar i;
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initial data_in =
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{72'h010101010101010101,
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72'h111111111111111111,
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72'h212121212121212121,
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72'h313131313131313131};
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for (i=0; i<4; i=i+1) begin : foo
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always @(posedge clk_str[i]) begin
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data_in[DAT_WIDTH*(i+1)-1:DAT_WIDTH*i] <=
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data_in[DAT_WIDTH*(i+1)-1:DAT_WIDTH*i] +
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72'h010101010101010101;
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end
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end
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initial begin
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start_harvest = 0;
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#1000
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@(negedge clk_sys);
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start_harvest = 1;
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@(posedge reporting);
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start_harvest = 0;
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@(negedge reporting);
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#1000
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@(negedge clk_sys);
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start_harvest = 1;
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@(posedge reporting);
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start_harvest = 0;
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@(negedge reporting);
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#1000
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@(negedge clk_sys);
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start_harvest = 1;
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@(posedge reporting);
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start_harvest = 0;
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end
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//////////////////////////////////////////////////
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// clock driver
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//////////////////////////////////////////////////
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always begin
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#5 clk_sys = ~clk_sys;
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end
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assign #1 clk_str[0] = clk_sys;
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assign #2 clk_str[1] = clk_sys;
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assign #3 clk_str[2] = clk_sys;
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assign #4 clk_str[3] = clk_sys;
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initial begin
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clk_sys = 0;
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arst_sys = 0;
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#1 arst_sys = 1;
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arst_str <= 4'b1111;
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@(negedge clk_sys) arst_sys = 0;
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@(negedge clk_str[0]) arst_str[0] = 0;
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@(negedge clk_str[1]) arst_str[1] = 0;
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@(negedge clk_str[2]) arst_str[2] = 0;
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@(negedge clk_str[3]) arst_str[3] = 0;
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end
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endmodule |