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127 lines
3.0 KiB
Systemverilog
127 lines
3.0 KiB
Systemverilog
// Copyright 2011 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 12-18-2008
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module twenty_to_eight_tb ();
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parameter WORD_LEN = 16;
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reg clk,arst;
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reg [8*WORD_LEN-1:0] din = 0;
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reg din_valid;
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wire din_ready;
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wire [20*WORD_LEN-1:0] middle;
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wire middle_valid,middle_ready;
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wire [8*WORD_LEN-1:0] dout;
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wire dout_valid;
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reg dout_ready;
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eight_to_twenty #(
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.WORD_LEN(WORD_LEN)
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)
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dut_8_20
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(
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.clk,.arst,
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.din,
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.din_valid,
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.din_ready,
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.dout(middle),
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.dout_ready(middle_ready),
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.dout_valid(middle_valid)
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);
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twenty_to_eight #(
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.WORD_LEN(WORD_LEN)
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)
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dut_20_8
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(
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.clk,.arst,
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.din(middle),
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.din_valid(middle_valid),
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.din_ready(middle_ready),
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.dout,
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.dout_ready,
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.dout_valid
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);
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// readback + verify
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reg fail = 0;
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integer k;
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reg [8*WORD_LEN-1:0] check;
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reg [WORD_LEN-1:0] exp = 1;
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always @(posedge clk) begin
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if (dout_valid & dout_ready) begin
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check = dout;
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for (k=0; k<8; k=k+1) begin
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if (check[WORD_LEN-1:0] != 0) begin
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if (exp != check[WORD_LEN-1:0]) begin
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$display ("Mismatch at time %d",$time);
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fail = 1;
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end
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exp = exp + 1;
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end
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check = check >> WORD_LEN;
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end
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end
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end
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reg last_din_valid, last_din_ready;
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always @(posedge clk) begin
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last_din_valid <= din_valid;
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last_din_ready <= din_ready;
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end
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// test stimulus
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integer n;
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reg [WORD_LEN-1:0] tmp = 0;
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always @(negedge clk) begin
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din_valid = $random;
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dout_ready = $random;
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if (last_din_valid & last_din_ready) begin
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for (n=0; n<8; n=n+1) begin
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tmp = tmp + 1;
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din = (din >> WORD_LEN) | (tmp << 7*WORD_LEN);
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end
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end
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end
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initial begin
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clk = 0;
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arst = 0;
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#1 arst = 1;
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@(negedge clk) arst = 0;
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end
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always begin
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#5 clk = ~clk;
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end
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endmodule
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