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103 lines
3.6 KiB
Verilog
103 lines
3.6 KiB
Verilog
// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 12-15-2008
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module pn2112_table (
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input [6:0] din,
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output reg [31:0] dout
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);
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always @(*) begin
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case (din)
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7'd 0 : dout = 32'hffffffff;
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7'd 1 : dout = 32'h02aaaaff;
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7'd 2 : dout = 32'haaaa8000;
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7'd 3 : dout = 32'h554aaaaa;
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7'd 4 : dout = 32'h0fffff55;
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7'd 5 : dout = 32'haaaa8000;
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7'd 6 : dout = 32'h557ffffa;
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7'd 7 : dout = 32'h55555755;
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7'd 8 : dout = 32'hfffe5555;
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7'd 9 : dout = 32'haa7ffff7;
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7'd 10 : dout = 32'he00002aa;
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7'd 11 : dout = 32'haaa8aaaa;
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7'd 12 : dout = 32'hffd5557a;
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7'd 13 : dout = 32'h00001fff;
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7'd 14 : dout = 32'hfff0aaaa;
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7'd 15 : dout = 32'h5055557f;
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7'd 16 : dout = 32'hd5557d55;
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7'd 17 : dout = 32'hfffffffd;
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7'd 18 : dout = 32'h08aaab1f;
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7'd 19 : dout = 32'h2aaa7000;
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7'd 20 : dout = 32'h551aaaa8;
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7'd 21 : dout = 32'h2dfffdd5;
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7'd 22 : dout = 32'haaaa8000;
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7'd 23 : dout = 32'h55f7ffe1;
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7'd 24 : dout = 32'h7d555ad5;
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7'd 25 : dout = 32'hfffab555;
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7'd 26 : dout = 32'ha8afffd5;
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7'd 27 : dout = 32'h0000002a;
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7'd 28 : dout = 32'haaa2aaab;
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7'd 29 : dout = 32'hfd555580;
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7'd 30 : dout = 32'ha8004aff;
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7'd 31 : dout = 32'hffd02aa8;
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7'd 32 : dout = 32'h4ab5557f;
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7'd 33 : dout = 32'ha555ff55;
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7'd 34 : dout = 32'hffd57ff0;
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7'd 35 : dout = 32'h282aafaf;
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7'd 36 : dout = 32'haaa88200;
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7'd 37 : dout = 32'h54e1aaaa;
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7'd 38 : dout = 32'hda7ff75d;
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7'd 39 : dout = 32'h4aa82800;
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7'd 40 : dout = 32'h577dffb0;
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7'd 41 : dout = 32'h7fd57885;
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7'd 42 : dout = 32'hffe1b555;
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7'd 43 : dout = 32'ha525ff5d;
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7'd 44 : dout = 32'he500282a;
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7'd 45 : dout = 32'h2a8082af;
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7'd 46 : dout = 32'hffd55752;
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7'd 47 : dout = 32'ha201ab1f;
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7'd 48 : dout = 32'h7f2adaa2;
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7'd 49 : dout = 32'h1fe557fd;
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7'd 50 : dout = 32'h075755d5;
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7'd 51 : dout = 32'hffd57fd0;
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7'd 52 : dout = 32'haaa2b554;
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7'd 53 : dout = 32'h02a5ff80;
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7'd 54 : dout = 32'h50554a80;
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7'd 55 : dout = 32'h2aafd7ff;
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7'd 56 : dout = 32'haaaaaa82;
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7'd 57 : dout = 32'h5dfffe4a;
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7'd 58 : dout = 32'hd5558fff;
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7'd 59 : dout = 32'h57b00057;
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7'd 60 : dout = 32'h87557dd5;
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7'd 61 : dout = 32'hffe02aaa;
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7'd 62 : dout = 32'h5a0800b4;
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7'd 63 : dout = 32'hd7ffdad5;
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7'd 64 : dout = 32'haa854aaf;
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7'd 65 : dout = 32'hfdfaa880;
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default : dout = 32'h0;
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endcase
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end
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endmodule
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